[v2,31/40] rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap

Submitted by Lucas De Marchi on Aug. 17, 2019, 9:38 a.m.

Details

Message ID 20190817093902.2171-32-lucas.demarchi@intel.com
State New
Headers show
Series "Tiger Lake batch 3" ( rev: 4 3 2 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Lucas De Marchi Aug. 17, 2019, 9:38 a.m.
From: Michel Thierry <michel.thierry@intel.com>

GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.

HSD: 399379
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 1 +
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 7 ++++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

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diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index edf194d23c6b..7719fadfe785 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -81,6 +81,7 @@ 
 #define   GT_DOORBELL_ENABLE		  (1<<0)
 
 #define GEN8_GTCR			_MMIO(0x4274)
+#define GEN12_GTCR			_MMIO(0xcee8)
 #define   GEN8_GTCR_INVALIDATE		  (1<<0)
 
 #define GUC_ARAT_C6DIS			_MMIO(0xA178)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6f6f0687d0bb..5cb9860cb02e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -131,9 +131,14 @@  static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
 	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
+	struct drm_i915_private *i915 = ggtt->vm.i915;
 
 	gen6_ggtt_invalidate(ggtt);
-	intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	if (INTEL_GEN(i915) >= 12)
+		intel_uncore_write_fw(uncore, GEN12_GTCR, GEN8_GTCR_INVALIDATE);
+	else
+		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)

Comments

Lucas De Marchi <lucas.demarchi@intel.com> writes:

> From: Michel Thierry <michel.thierry@intel.com>
>
> GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
> this is to make space for global MOCS registers.
>
> HSD: 399379
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 1 +
>  drivers/gpu/drm/i915/i915_gem_gtt.c        | 7 ++++++-
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
> index edf194d23c6b..7719fadfe785 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
> @@ -81,6 +81,7 @@
>  #define   GT_DOORBELL_ENABLE		  (1<<0)
>  
>  #define GEN8_GTCR			_MMIO(0x4274)
> +#define GEN12_GTCR			_MMIO(0xcee8)

This naming is a bit off. The register is not called
the same even tho it seems to serve the same purpose.
We usually try to follow the bspec naming here
for easier

But as this is contained in guc_reg.h I do not
insist. But please consider changing it.

With or without reg name changed to be GUC_TLB_INV_CR,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>  #define   GEN8_GTCR_INVALIDATE		  (1<<0)
>
>  #define GUC_ARAT_C6DIS			_MMIO(0xA178)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 6f6f0687d0bb..5cb9860cb02e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -131,9 +131,14 @@ static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
>  static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
>  {
>  	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
> +	struct drm_i915_private *i915 = ggtt->vm.i915;
>  
>  	gen6_ggtt_invalidate(ggtt);
> -	intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> +	if (INTEL_GEN(i915) >= 12)
> +		intel_uncore_write_fw(uncore, GEN12_GTCR, GEN8_GTCR_INVALIDATE);
> +	else
> +		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>  }
>  
>  static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
> -- 
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, Aug 22, 2019 at 04:28:15PM +0300, Mika Kuoppala wrote:
>Lucas De Marchi <lucas.demarchi@intel.com> writes:
>
>> From: Michel Thierry <michel.thierry@intel.com>
>>
>> GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
>> this is to make space for global MOCS registers.
>>
>> HSD: 399379
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 1 +
>>  drivers/gpu/drm/i915/i915_gem_gtt.c        | 7 ++++++-
>>  2 files changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
>> index edf194d23c6b..7719fadfe785 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
>> @@ -81,6 +81,7 @@
>>  #define   GT_DOORBELL_ENABLE		  (1<<0)
>>
>>  #define GEN8_GTCR			_MMIO(0x4274)
>> +#define GEN12_GTCR			_MMIO(0xcee8)
>
>This naming is a bit off. The register is not called
>the same even tho it seems to serve the same purpose.
>We usually try to follow the bspec naming here
>for easier
>
>But as this is contained in guc_reg.h I do not
>insist. But please consider changing it.
>
>With or without reg name changed to be GUC_TLB_INV_CR,

well... In general what I see is that we stick to the register name on
the first platform. Anyway, I will change it.

>Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

thanks
Lucas De Marchi

>
>>  #define   GEN8_GTCR_INVALIDATE		  (1<<0)
>>
>>  #define GUC_ARAT_C6DIS			_MMIO(0xA178)
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 6f6f0687d0bb..5cb9860cb02e 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -131,9 +131,14 @@ static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
>>  static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
>>  {
>>  	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
>> +	struct drm_i915_private *i915 = ggtt->vm.i915;
>>
>>  	gen6_ggtt_invalidate(ggtt);
>> -	intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> +
>> +	if (INTEL_GEN(i915) >= 12)
>> +		intel_uncore_write_fw(uncore, GEN12_GTCR, GEN8_GTCR_INVALIDATE);
>> +	else
>> +		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>>  }
>>
>>  static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx