[v2,40/40] drm/i915/tgl: Gen-12 media compression

Submitted by Lucas De Marchi on Aug. 17, 2019, 9:39 a.m.

Details

Message ID 20190817093902.2171-41-lucas.demarchi@intel.com
State New
Headers show
Series "Tiger Lake batch 3" ( rev: 4 3 2 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Lucas De Marchi Aug. 17, 2019, 9:39 a.m.
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display can decompress surfaces compressed by the media engine.
Detect the modifier corresponding to media compression to enable
decompression for YUV and ARGB packed formats. A new modifier is added
so that the driver can distinguish between media and render compressed
buffers. Unlike render decompression, plane 6 and  plane 7 do not support
media decompression.

v2: Fix checkpatch warnings on code style (Lucas)

Bspec: 29695

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 23 +++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_sprite.c  | 20 +++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 3 files changed, 37 insertions(+), 7 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 190adbffe055..18ff4631f873 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1913,6 +1913,7 @@  intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 			return 128;
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		if (color_plane == 1)
 			return cpp;
 		/* fall through */
@@ -2050,6 +2051,7 @@  static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 			return 256 * 1024;
 		return 0;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return 4 * 4 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2248,8 +2250,15 @@  static u32 intel_adjust_tile_offset(int *x, int *y,
 
 static bool is_surface_linear(u64 modifier, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR ||
-	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+	switch (modifier) {
+	case DRM_FORMAT_MOD_LINEAR:
+		return true;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return color_plane == 1;
+	default:
+		return false;
+	}
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2437,6 +2446,7 @@  static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2510,6 +2520,7 @@  intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 					  ARRAY_SIZE(skl_ccs_formats),
 					  cmd->pixel_format);
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return lookup_format_info(gen12_ccs_formats,
 					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
@@ -2521,6 +2532,7 @@  intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 bool is_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
@@ -4093,6 +4105,8 @@  static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9870,6 +9884,8 @@  skylake_get_initial_plane_config(struct intel_crtc *crtc,
 			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
 				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
 				I915_FORMAT_MOD_Y_TILED_CCS;
+		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
@@ -15740,7 +15756,8 @@  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		 * The main surface pitch must be paded to a multiple of four
 		 * tile widths.
 		 */
-		if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
+		if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+		     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) &&
 		    i == 0)
 			stride_alignment *= 4;
 
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 73d32017be89..5df3a899068e 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1749,7 +1749,8 @@  static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2163,6 +2164,7 @@  static const u64 skl_plane_format_modifiers_ccs[] = {
 
 static const u64 gen12_plane_format_modifiers_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2320,7 +2322,13 @@  static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 					     u32 format, u64 modifier)
 {
+	struct intel_plane *plane = to_intel_plane(_plane);
+
 	switch (modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		if (plane->id >= PLANE_SPRITE4)
+			return false;
+		/* fall through */
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2338,14 +2346,18 @@  static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (is_ccs_modifier(modifier))
 			return true;
 		/* fall through */
-	case DRM_FORMAT_RGB565:
-	case DRM_FORMAT_XRGB2101010:
-	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+			return true;
+		/* fall through */
+	/* TODO: Media decompression does support NV12 */
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_C8:
 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
 		    modifier == I915_FORMAT_MOD_X_TILED ||
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c402239bba7..7ff207815087 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6788,6 +6788,7 @@  enum {
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
+#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)

Comments

On Sat, 2019-08-17 at 02:39 -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> 

> Gen-12 display can decompress surfaces compressed by the media

> engine.

> Detect the modifier corresponding to media compression to enable

> decompression for YUV and ARGB packed formats. A new modifier is

> added

> so that the driver can distinguish between media and render

> compressed

> buffers. Unlike render decompression, plane 6 and  plane 7 do not

> support

> media decompression.

> 

> v2: Fix checkpatch warnings on code style (Lucas)

> 

> Bspec: 29695

> 

> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

> ---

>  drivers/gpu/drm/i915/display/intel_display.c | 23 +++++++++++++++++-

> --

>  drivers/gpu/drm/i915/display/intel_sprite.c  | 20 +++++++++++++----

>  drivers/gpu/drm/i915/i915_reg.h              |  1 +

>  3 files changed, 37 insertions(+), 7 deletions(-)

> 

> diff --git a/drivers/gpu/drm/i915/display/intel_display.c

> b/drivers/gpu/drm/i915/display/intel_display.c

> index 190adbffe055..18ff4631f873 100644

> --- a/drivers/gpu/drm/i915/display/intel_display.c

> +++ b/drivers/gpu/drm/i915/display/intel_display.c

> @@ -1913,6 +1913,7 @@ intel_tile_width_bytes(const struct

> drm_framebuffer *fb, int color_plane)

>  			return 128;

>  		/* fall through */

>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:

> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

>  		if (color_plane == 1)

>  			return cpp;

>  		/* fall through */

> @@ -2050,6 +2051,7 @@ static unsigned int intel_surf_alignment(const

> struct drm_framebuffer *fb,

>  			return 256 * 1024;

>  		return 0;

>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:

> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

>  		return 4 * 4 * 1024;

>  	case I915_FORMAT_MOD_Y_TILED_CCS:

>  	case I915_FORMAT_MOD_Yf_TILED_CCS:

> @@ -2248,8 +2250,15 @@ static u32 intel_adjust_tile_offset(int *x,

> int *y,

>  

>  static bool is_surface_linear(u64 modifier, int color_plane)

>  {

> -	return modifier == DRM_FORMAT_MOD_LINEAR ||

> -	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&

> color_plane == 1);

> +	switch (modifier) {

> +	case DRM_FORMAT_MOD_LINEAR:

> +		return true;

> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:

> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

> +		return color_plane == 1;

> +	default:

> +		return false;

> +	}

>  }

>  

>  static u32 intel_adjust_aligned_offset(int *x, int *y,

> @@ -2437,6 +2446,7 @@ static unsigned int

> intel_fb_modifier_to_tiling(u64 fb_modifier)

>  	case I915_FORMAT_MOD_Y_TILED:

>  	case I915_FORMAT_MOD_Y_TILED_CCS:

>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:

> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

>  		return I915_TILING_Y;

>  	default:

>  		return I915_TILING_NONE;

> @@ -2510,6 +2520,7 @@ intel_get_format_info(const struct

> drm_mode_fb_cmd2 *cmd)

>  					  ARRAY_SIZE(skl_ccs_formats),

>  					  cmd->pixel_format);

>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:

> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

>  		return lookup_format_info(gen12_ccs_formats,

>  					  ARRAY_SIZE(gen12_ccs_formats)

> ,

>  					  cmd->pixel_format);

> @@ -2521,6 +2532,7 @@ intel_get_format_info(const struct

> drm_mode_fb_cmd2 *cmd)

>  bool is_ccs_modifier(u64 modifier)

>  {

>  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||

> +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||

>  	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||

>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;

>  }

> @@ -4093,6 +4105,8 @@ static u32 skl_plane_ctl_tiling(u64

> fb_modifier)

>  		/* fall through */

>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:

>  		return PLANE_CTL_TILED_Y |

> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;

> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

> +		return PLANE_CTL_TILED_Y |

> PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;

>  	case I915_FORMAT_MOD_Yf_TILED:

>  		return PLANE_CTL_TILED_YF;

>  	case I915_FORMAT_MOD_Yf_TILED_CCS:

> @@ -9870,6 +9884,8 @@ skylake_get_initial_plane_config(struct

> intel_crtc *crtc,

>  			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?

>  				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :

>  				I915_FORMAT_MOD_Y_TILED_CCS;

> +		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)

> +			fb->modifier =

> I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;

>  		else

>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;

>  		break;

> @@ -15740,7 +15756,8 @@ static int intel_framebuffer_init(struct

> intel_framebuffer *intel_fb,

>  		 * The main surface pitch must be paded to a multiple

> of four

>  		 * tile widths.

>  		 */

> -		if (fb->modifier ==

> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&

> +		if ((fb->modifier ==

> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||

> +		     fb->modifier ==

> I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) &&

>  		    i == 0)

>  			stride_alignment *= 4;

>  

> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c

> b/drivers/gpu/drm/i915/display/intel_sprite.c

> index 73d32017be89..5df3a899068e 100644

> --- a/drivers/gpu/drm/i915/display/intel_sprite.c

> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c

> @@ -1749,7 +1749,8 @@ static int skl_plane_check_fb(const struct

> intel_crtc_state *crtc_state,

>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||

>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||

>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||

> -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {

> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||

> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {

>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID

> mode\n");

>  		return -EINVAL;

>  	}

> @@ -2163,6 +2164,7 @@ static const u64

> skl_plane_format_modifiers_ccs[] = {

>  

>  static const u64 gen12_plane_format_modifiers_ccs[] = {

>  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,

> +	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,

>  	I915_FORMAT_MOD_Y_TILED,

>  	I915_FORMAT_MOD_X_TILED,

>  	DRM_FORMAT_MOD_LINEAR,

> @@ -2320,7 +2322,13 @@ static bool

> skl_plane_format_mod_supported(struct drm_plane *_plane,

>  static bool gen12_plane_format_mod_supported(struct drm_plane

> *_plane,

>  					     u32 format, u64 modifier)

>  {

> +	struct intel_plane *plane = to_intel_plane(_plane);

> +

>  	switch (modifier) {

> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

> +		if (plane->id >= PLANE_SPRITE4)

> +			return false;

> +		/* fall through */

>  	case DRM_FORMAT_MOD_LINEAR:

>  	case I915_FORMAT_MOD_X_TILED:

>  	case I915_FORMAT_MOD_Y_TILED:

> @@ -2338,14 +2346,18 @@ static bool

> gen12_plane_format_mod_supported(struct drm_plane *_plane,

>  		if (is_ccs_modifier(modifier))

>  			return true;

>  		/* fall through */

> -	case DRM_FORMAT_RGB565:

> -	case DRM_FORMAT_XRGB2101010:

> -	case DRM_FORMAT_XBGR2101010:

>  	case DRM_FORMAT_YUYV:

>  	case DRM_FORMAT_YVYU:

>  	case DRM_FORMAT_UYVY:

>  	case DRM_FORMAT_VYUY:

> +		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)

> +			return true;

> +		/* fall through */

> +	/* TODO: Media decompression does support NV12 */

>  	case DRM_FORMAT_NV12:

> +	case DRM_FORMAT_RGB565:

> +	case DRM_FORMAT_XRGB2101010:

> +	case DRM_FORMAT_XBGR2101010:

>  	case DRM_FORMAT_C8:

>  		if (modifier == DRM_FORMAT_MOD_LINEAR ||

>  		    modifier == I915_FORMAT_MOD_X_TILED ||

> diff --git a/drivers/gpu/drm/i915/i915_reg.h

> b/drivers/gpu/drm/i915/i915_reg.h

> index 4c402239bba7..7ff207815087 100644

> --- a/drivers/gpu/drm/i915/i915_reg.h

> +++ b/drivers/gpu/drm/i915/i915_reg.h

> @@ -6788,6 +6788,7 @@ enum {

>  #define   PLANE_CTL_TILED_Y			(4 << 10)

>  #define   PLANE_CTL_TILED_YF			(5 << 10)

>  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)

> +#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /*

> TGL+ */

>  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /*

> Pre-GLK */

>  #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)

>  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)


Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>