[30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap

Submitted by Lucas De Marchi on Aug. 16, 2019, 8:04 a.m.

Details

Message ID 20190816080503.28594-31-lucas.demarchi@intel.com
State New
Headers show
Series "Tiger Lake batch 3" ( rev: 1 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Lucas De Marchi Aug. 16, 2019, 8:04 a.m.
From: Michel Thierry <michel.thierry@intel.com>

GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.

HSD: 399379
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 1 +
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 8 ++++++--
 2 files changed, 7 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index edf194d23c6b..7719fadfe785 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -81,6 +81,7 @@ 
 #define   GT_DOORBELL_ENABLE		  (1<<0)
 
 #define GEN8_GTCR			_MMIO(0x4274)
+#define GEN12_GTCR			_MMIO(0xcee8)
 #define   GEN8_GTCR_INVALIDATE		  (1<<0)
 
 #define GUC_ARAT_C6DIS			_MMIO(0xA178)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 536eadf095fe..76af40d23f09 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -130,10 +130,14 @@  static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 
 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
-	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
+	struct drm_i915_private *i915 = ggtt->vm.i915;
+	struct intel_uncore *uncore = &i915->uncore;
 
 	gen6_ggtt_invalidate(ggtt);
-	intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+	if (INTEL_GEN(i915) >= 12)
+		intel_uncore_write_fw(uncore, GEN12_GTCR, GEN8_GTCR_INVALIDATE);
+	else
+		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)