[26/39] HACK: drm/i915/tgl: Gen12 render context size

Submitted by Lucas De Marchi on Aug. 16, 2019, 8:04 a.m.

Details

Message ID 20190816080503.28594-27-lucas.demarchi@intel.com
State Accepted
Commit 0aa5427a7fd3349d5d77ee8be8e47d15705d4f0e
Headers show
Series "Tiger Lake batch 3" ( rev: 1 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Lucas De Marchi Aug. 16, 2019, 8:04 a.m.
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Re-use Gen11 context size for now.

[ Lucas: add HACK since this is a temporary patch that needs to be
  confirmed: we need to check BSpec 46255 and recompute ]

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
 1 file changed, 1 insertion(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d20750e420c0..d398d80d4a0d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -164,6 +164,7 @@  u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
 		default:
 			MISSING_CASE(INTEL_GEN(dev_priv));
 			return DEFAULT_LR_CONTEXT_RENDER_SIZE;
+		case 12:
 		case 11:
 			return GEN11_LR_CONTEXT_RENDER_SIZE;
 		case 10: