[v2,5/5] drm/amdgpu: Use new mode2 reset interface for RV.

Submitted by Grodzovsky, Andrey on Aug. 14, 2019, 8:40 p.m.

Details

Message ID 1565815217-9533-6-git-send-email-andrey.grodzovsky@amd.com
State New
Headers show
Series "Add mode 2 GPU reset for RV2/Picasso" ( rev: 2 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Grodzovsky, Andrey Aug. 14, 2019, 8:40 p.m.
v2:
Check ppfuncs pointer for NULL

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c         | 25 +++++++++++++++++--------
 2 files changed, 18 insertions(+), 8 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2752773..02b3e7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3524,6 +3524,7 @@  bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
 		case CHIP_VEGA20:
 		case CHIP_VEGA10:
 		case CHIP_VEGA12:
+		case CHIP_RAVEN:
 			break;
 		default:
 			goto disabled;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c2d324d..77e6799 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -508,6 +508,15 @@  static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 	return 0;
 }
 
+static int soc15_mode2_reset(struct amdgpu_device *adev)
+{
+	if (!adev->powerplay.pp_funcs ||
+	    !adev->powerplay.pp_funcs->asic_reset_mode_2)
+		return -ENOENT;
+
+	return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle);
+}
+
 static enum amd_reset_method
 soc15_asic_reset_method(struct amdgpu_device *adev)
 {
@@ -546,14 +555,14 @@  soc15_asic_reset_method(struct amdgpu_device *adev)
 
 static int soc15_asic_reset(struct amdgpu_device *adev)
 {
-	int ret;
-
-	if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
-		ret = soc15_asic_baco_reset(adev);
-	else
-		ret = soc15_asic_mode1_reset(adev);
-
-	return ret;
+	switch (soc15_asic_reset_method(adev)) {
+		case AMD_RESET_METHOD_BACO:
+			return soc15_asic_baco_reset(adev);
+		case AMD_RESET_METHOD_MODE2:
+			return soc15_mode2_reset(adev);
+		default:
+			return soc15_asic_mode1_reset(adev);
+	}
 }
 
 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

Comments

Series is Reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----

> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of

> Andrey Grodzovsky

> Sent: Thursday, August 15, 2019 4:40 AM

> To: amd-gfx@lists.freedesktop.org

> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Grodzovsky,

> Andrey <Andrey.Grodzovsky@amd.com>; Quan, Evan

> <Evan.Quan@amd.com>; S, Shirish <Shirish.S@amd.com>

> Subject: [PATCH v2 5/5] drm/amdgpu: Use new mode2 reset interface for RV.

> 

> v2:

> Check ppfuncs pointer for NULL

> 

> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>

> ---

>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 +

>  drivers/gpu/drm/amd/amdgpu/soc15.c         | 25 +++++++++++++++++-------

> -

>  2 files changed, 18 insertions(+), 8 deletions(-)

> 

> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

> index 2752773..02b3e7d 100644

> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

> @@ -3524,6 +3524,7 @@ bool amdgpu_device_should_recover_gpu(struct

> amdgpu_device *adev)

>  		case CHIP_VEGA20:

>  		case CHIP_VEGA10:

>  		case CHIP_VEGA12:

> +		case CHIP_RAVEN:

>  			break;

>  		default:

>  			goto disabled;

> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

> b/drivers/gpu/drm/amd/amdgpu/soc15.c

> index c2d324d..77e6799 100644

> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c

> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c

> @@ -508,6 +508,15 @@ static int soc15_asic_baco_reset(struct

> amdgpu_device *adev)

>  	return 0;

>  }

> 

> +static int soc15_mode2_reset(struct amdgpu_device *adev) {

> +	if (!adev->powerplay.pp_funcs ||

> +	    !adev->powerplay.pp_funcs->asic_reset_mode_2)

> +		return -ENOENT;

> +

> +	return

> +adev->powerplay.pp_funcs->asic_reset_mode_2(adev-

> >powerplay.pp_handle);

> +}

> +

>  static enum amd_reset_method

>  soc15_asic_reset_method(struct amdgpu_device *adev)  { @@ -546,14

> +555,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev)

> 

>  static int soc15_asic_reset(struct amdgpu_device *adev)  {

> -	int ret;

> -

> -	if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)

> -		ret = soc15_asic_baco_reset(adev);

> -	else

> -		ret = soc15_asic_mode1_reset(adev);

> -

> -	return ret;

> +	switch (soc15_asic_reset_method(adev)) {

> +		case AMD_RESET_METHOD_BACO:

> +			return soc15_asic_baco_reset(adev);

> +		case AMD_RESET_METHOD_MODE2:

> +			return soc15_mode2_reset(adev);

> +		default:

> +			return soc15_asic_mode1_reset(adev);

> +	}

>  }

> 

>  /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

> --

> 2.7.4

> 

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