[v2,2/5] drm/amd/powerplay: add mode2 reset callback for pp_smu_mgr

Submitted by Andrey Grodzovsky on Aug. 14, 2019, 8:40 p.m.

Details

Message ID 1565815217-9533-3-git-send-email-andrey.grodzovsky@amd.com
State Accepted
Commit d6c23e6f1374180dc1197a1d25323ec68bd1e04c
Headers show
Series "Add mode 2 GPU reset for RV2/Picasso" ( rev: 2 ) in AMD X.Org drivers

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Commit Message

Andrey Grodzovsky Aug. 14, 2019, 8:40 p.m. 
Also define reset modes (0, 1 and 2)

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 9 +++++++++
 1 file changed, 9 insertions(+)

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diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 07fd64a..abeff15 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -189,6 +189,14 @@  struct phm_vce_clock_voltage_dependency_table {
 	struct phm_vce_clock_voltage_dependency_record entries[1];
 };
 
+
+enum SMU_ASIC_RESET_MODE
+{
+    SMU_ASIC_RESET_MODE_0,
+    SMU_ASIC_RESET_MODE_1,
+    SMU_ASIC_RESET_MODE_2,
+};
+
 struct pp_smumgr_func {
 	char *name;
 	int (*smu_init)(struct pp_hwmgr  *hwmgr);
@@ -345,6 +353,7 @@  struct pp_hwmgr_func {
 	int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
 	int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
 	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
+	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
 };
 
 struct pp_table_func {