[2/3] drm/amd/powerplay: Add support for mode2 ASIC reset.

Submitted by Grodzovsky, Andrey on Aug. 14, 2019, 7:53 p.m.

Details

Message ID 1565812414-26117-3-git-send-email-andrey.grodzovsky@amd.com
State New
Headers show
Series "Add mode 2 GPU reset for RV2/Picasso" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Grodzovsky, Andrey Aug. 14, 2019, 7:53 p.m.
Mode 2 GPU reset should be done by sending message to SMU.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 21 +++++++++++++++++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c |  7 +++++++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |  9 +++++++++
 4 files changed, 38 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index bba1291..9c477b4 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -310,6 +310,7 @@  struct amd_pm_funcs {
 	int (*set_asic_baco_state)(void *handle, int state);
 	int (*get_ppfeature_status)(void *handle, char *buf);
 	int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
+	int (*asic_reset_mod_2)(void *handle);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 2e3d9ef6..becca76 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1508,6 +1508,26 @@  static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
 	return ret;
 }
 
+static int pp_asic_reset_mode_2(void *handle)
+{
+	struct pp_hwmgr *hwmgr = handle;
+		int ret = 0;
+
+	if (!hwmgr || !hwmgr->pm_en)
+		return -EINVAL;
+
+	if (hwmgr->hwmgr_func->asic_reset == NULL) {
+		pr_info_ratelimited("%s was not implemented.\n", __func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&hwmgr->smu_lock);
+	ret = hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASCI_RESET_MODE_2);
+	mutex_unlock(&hwmgr->smu_lock);
+
+	return ret;
+}
+
 static const struct amd_pm_funcs pp_dpm_funcs = {
 	.load_firmware = pp_dpm_load_fw,
 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1564,4 +1584,5 @@  static const struct amd_pm_funcs pp_dpm_funcs = {
 	.set_asic_baco_state = pp_set_asic_baco_state,
 	.get_ppfeature_status = pp_get_ppfeature_status,
 	.set_ppfeature_status = pp_set_ppfeature_status,
+	.asic_reset_mod_2 = pp_asic_reset_mode_2,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 18e780f..1115761 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1311,6 +1311,12 @@  static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uin
 	return 0;
 }
 
+static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
+{
+	return smum_send_msg_to_smc_with_parameter(hwmgr,
+						   PPSMC_MSG_DeviceDriverReset,
+						   mode);
+}
 
 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
 	.backend_init = smu10_hwmgr_backend_init,
@@ -1355,6 +1361,7 @@  static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
 	.set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
 	.get_power_profile_mode = smu10_get_power_profile_mode,
 	.set_power_profile_mode = smu10_set_power_profile_mode,
+	.asic_reset = smu10_asic_reset,
 };
 
 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 07fd64a..d583568 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -189,6 +189,14 @@  struct phm_vce_clock_voltage_dependency_table {
 	struct phm_vce_clock_voltage_dependency_record entries[1];
 };
 
+
+enum SMU_ASIC_RESET_MODE
+{
+    SMU_ASCI_RESET_MODE_0,
+    SMU_ASCI_RESET_MODE_1,
+    SMU_ASCI_RESET_MODE_2,
+};
+
 struct pp_smumgr_func {
 	char *name;
 	int (*smu_init)(struct pp_hwmgr  *hwmgr);
@@ -345,6 +353,7 @@  struct pp_hwmgr_func {
 	int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
 	int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
 	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
+	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
 };
 
 struct pp_table_func {

Comments

On Wed, Aug 14, 2019 at 3:54 PM Andrey Grodzovsky
<andrey.grodzovsky@amd.com> wrote:
>
> Mode 2 GPU reset should be done by sending message to SMU.
>
> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>

I think this should be 3 patches:
1. add the pp_smumgr_func callback
2. add the smu10 implementation
3. add the amd_pm_funcs implementation

Also a couple of typos below.

> ---
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 21 +++++++++++++++++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c |  7 +++++++
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |  9 +++++++++
>  4 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index bba1291..9c477b4 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -310,6 +310,7 @@ struct amd_pm_funcs {
>         int (*set_asic_baco_state)(void *handle, int state);
>         int (*get_ppfeature_status)(void *handle, char *buf);
>         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
> +       int (*asic_reset_mod_2)(void *handle);

typo: mod -> mode

>  };
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 2e3d9ef6..becca76 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1508,6 +1508,26 @@ static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
>         return ret;
>  }
>
> +static int pp_asic_reset_mode_2(void *handle)
> +{
> +       struct pp_hwmgr *hwmgr = handle;
> +               int ret = 0;
> +
> +       if (!hwmgr || !hwmgr->pm_en)
> +               return -EINVAL;
> +
> +       if (hwmgr->hwmgr_func->asic_reset == NULL) {
> +               pr_info_ratelimited("%s was not implemented.\n", __func__);
> +               return -EINVAL;
> +       }
> +
> +       mutex_lock(&hwmgr->smu_lock);
> +       ret = hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASCI_RESET_MODE_2);
> +       mutex_unlock(&hwmgr->smu_lock);
> +
> +       return ret;
> +}
> +
>  static const struct amd_pm_funcs pp_dpm_funcs = {
>         .load_firmware = pp_dpm_load_fw,
>         .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
> @@ -1564,4 +1584,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
>         .set_asic_baco_state = pp_set_asic_baco_state,
>         .get_ppfeature_status = pp_get_ppfeature_status,
>         .set_ppfeature_status = pp_set_ppfeature_status,
> +       .asic_reset_mod_2 = pp_asic_reset_mode_2,
>  };
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 18e780f..1115761 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1311,6 +1311,12 @@ static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uin
>         return 0;
>  }
>
> +static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
> +{
> +       return smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                                  PPSMC_MSG_DeviceDriverReset,
> +                                                  mode);
> +}
>
>  static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
>         .backend_init = smu10_hwmgr_backend_init,
> @@ -1355,6 +1361,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
>         .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
>         .get_power_profile_mode = smu10_get_power_profile_mode,
>         .set_power_profile_mode = smu10_set_power_profile_mode,
> +       .asic_reset = smu10_asic_reset,
>  };
>
>  int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 07fd64a..d583568 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -189,6 +189,14 @@ struct phm_vce_clock_voltage_dependency_table {
>         struct phm_vce_clock_voltage_dependency_record entries[1];
>  };
>
> +
> +enum SMU_ASIC_RESET_MODE
> +{
> +    SMU_ASCI_RESET_MODE_0,
> +    SMU_ASCI_RESET_MODE_1,
> +    SMU_ASCI_RESET_MODE_2,

typo: ASCI -> ASIC

> +};
> +
>  struct pp_smumgr_func {
>         char *name;
>         int (*smu_init)(struct pp_hwmgr  *hwmgr);
> @@ -345,6 +353,7 @@ struct pp_hwmgr_func {
>         int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
>         int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
>         int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
> +       int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
>  };
>
>  struct pp_table_func {
> --
> 2.7.4
>
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