[1/3] drm/amd/powerplay: Fix meaning of 0x1E PPSMC_MSG

Submitted by Andrey Grodzovsky on Aug. 14, 2019, 7:53 p.m.

Details

Message ID 1565812414-26117-2-git-send-email-andrey.grodzovsky@amd.com
State Accepted
Commit e84fb7bca63761c42201da7783f8a3a3abd8287b
Headers show
Series "Add mode 2 GPU reset for RV2/Picasso" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Andrey Grodzovsky Aug. 14, 2019, 7:53 p.m.
By comparing to windows it means ASIC reset.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

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diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index 90879e4..df4677d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -59,7 +59,7 @@ 
 #define PPSMC_MSG_SetDriverDramAddrLow          0x1B
 #define PPSMC_MSG_TransferTableSmu2Dram         0x1C
 #define PPSMC_MSG_TransferTableDram2Smu         0x1D
-#define PPSMC_MSG_ControlGfxRM                  0x1E
+#define PPSMC_MSG_DeviceDriverReset             0x1E
 #define PPSMC_MSG_SetGfxclkOverdriveByFreqVid   0x1F
 #define PPSMC_MSG_SetHardMinDcefclkByFreq       0x20
 #define PPSMC_MSG_SetHardMinSocclkByFreq        0x21

Comments

On Wed, Aug 14, 2019 at 3:53 PM Andrey Grodzovsky
<andrey.grodzovsky@amd.com> wrote:
>
> By comparing to windows it means ASIC reset.
>
> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> index 90879e4..df4677d 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> @@ -59,7 +59,7 @@
>  #define PPSMC_MSG_SetDriverDramAddrLow          0x1B
>  #define PPSMC_MSG_TransferTableSmu2Dram         0x1C
>  #define PPSMC_MSG_TransferTableDram2Smu         0x1D
> -#define PPSMC_MSG_ControlGfxRM                  0x1E
> +#define PPSMC_MSG_DeviceDriverReset             0x1E
>  #define PPSMC_MSG_SetGfxclkOverdriveByFreqVid   0x1F
>  #define PPSMC_MSG_SetHardMinDcefclkByFreq       0x20
>  #define PPSMC_MSG_SetHardMinSocclkByFreq        0x21
> --
> 2.7.4
>
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