[07/15] drm/i915/dsb: Register definition of DSB registers.

Submitted by Animesh Manna on Aug. 12, 2019, 8:06 a.m.

Details

Message ID 20190812080655.27535-7-animesh.manna@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX - Try Bot

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Commit Message

Animesh Manna Aug. 12, 2019, 8:06 a.m.
Added key register definitions of DSB.

dsb-ctrl register is required to enable dsb-engine.

head-ptr register hold the head of buffer address from where the
execution will start.

Programming tail-ptr register is a trigger point to start execution.

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6fac0b4287fe..ce492bc026f6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11610,4 +11610,19 @@  enum skl_power_gate {
 #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
 #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))
 
+/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE		0x70B00
+#define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
+					 (pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD_PTR(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL_PTR(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
+#define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define   DSB_ENABLE			(1 << 31)
+#define   DSB_BUFFER_REITERATE		(1 << 29)
+#define   DSB_WAIT_FOR_VBLANK		(1 << 28)
+#define   DSB_WAIT_FOR_LINE_IN_RANGE	(1 << 27)
+#define   DSB_HALT			(1 << 16)
+#define   DSB_NON_POSTED_ENABLE		(1 << 8)
+#define   DSB_STATUS			(1 << 0)
+
 #endif /* _I915_REG_H_ */