[02/15] drm/i915/dsb: DSB context creation.

Submitted by Animesh Manna on Aug. 12, 2019, 8:06 a.m.

Details

Message ID 20190812080655.27535-2-animesh.manna@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX - Try Bot

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Commit Message

Animesh Manna Aug. 12, 2019, 8:06 a.m.
The function will internally get the gem buffer from global GTT
which is mapped in cpu domain to feed the data + opcode for DSB engine.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |  1 +
 .../drm/i915/display/intel_display_types.h    |  4 ++
 drivers/gpu/drm/i915/i915_drv.h               |  1 +
 drivers/gpu/drm/i915/intel_dsb.c              | 66 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsb.h              | 31 +++++++++
 5 files changed, 103 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_dsb.c
 create mode 100644 drivers/gpu/drm/i915/intel_dsb.h

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diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d3ca46dc54ae..06458834fba7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -50,6 +50,7 @@  i915-y += i915_drv.o \
 	  i915_utils.o \
 	  intel_csr.o \
 	  intel_device_info.o \
+	  intel_dsb.o \
 	  intel_pch.o \
 	  intel_pm.o \
 	  intel_runtime_pm.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a88ec9aa9ca0..56e91f04c9b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1025,6 +1025,10 @@  struct intel_crtc {
 
 	/* scalers available on this crtc */
 	int num_scalers;
+
+	/* per pipe DSB related info */
+	struct intel_dsb dsb[MAX_DSB_PER_PIPE];
+	int dsb_in_use;
 };
 
 struct intel_plane {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 29cb320fccf2..d8cf8ad94b30 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -81,6 +81,7 @@ 
 #include "gt/uc/intel_uc.h"
 
 #include "intel_device_info.h"
+#include "intel_dsb.h"
 #include "intel_pch.h"
 #include "intel_runtime_pm.h"
 #include "intel_uncore.h"
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
new file mode 100644
index 000000000000..f404321ff665
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -0,0 +1,66 @@ 
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ */
+
+#include "i915_drv.h"
+#include "display/intel_display_types.h"
+
+#define DSB_BUF_SIZE    (2 * PAGE_SIZE)
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *i915 = to_i915(dev);
+	struct drm_i915_gem_object *obj;
+	struct i915_vma *vma;
+	struct intel_dsb *dsb;
+	intel_wakeref_t wakeref;
+	int i;
+
+	WARN_ON(crtc->dsb_in_use >= MAX_DSB_PER_PIPE);
+
+	for (i = 0; i < MAX_DSB_PER_PIPE; i++) {
+		if (!crtc->dsb[i].cmd_buf) {
+			dsb = &crtc->dsb[i];
+			dsb->id = i;
+		}
+	}
+
+	dsb = &crtc->dsb[crtc->dsb_in_use];
+	dsb->crtc = crtc;
+	if (!HAS_DSB(i915))
+		return dsb;
+
+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+	mutex_lock(&i915->drm.struct_mutex);
+
+	obj = i915_gem_object_create_shmem(i915, DSB_BUF_SIZE);
+	if (IS_ERR(obj))
+		goto err;
+
+	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+	if (IS_ERR(vma)) {
+		DRM_DEBUG_KMS("Vma creation failed.\n");
+		i915_gem_object_put(obj);
+		goto err;
+	}
+
+	dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+	if (IS_ERR(dsb->cmd_buf)) {
+		DRM_DEBUG_KMS("Command buffer creation failed.\n");
+		dsb->cmd_buf = NULL;
+		goto err;
+	}
+	crtc->dsb_in_use++;
+	dsb->cmd_buf_head = (uintptr_t)i915_ggtt_offset(vma);
+	dsb->vma = vma;
+
+	memset(dsb->cmd_buf, 0, DSB_BUF_SIZE);
+err:
+	mutex_unlock(&i915->drm.struct_mutex);
+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+	return dsb;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsb.h b/drivers/gpu/drm/i915/intel_dsb.h
new file mode 100644
index 000000000000..50a2a6590a71
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsb.h
@@ -0,0 +1,31 @@ 
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_DSB_H
+#define _INTEL_DSB_H
+
+struct intel_crtc;
+struct i915_vma;
+
+enum dsb_id {
+	INVALID_DSB = -1,
+	DSB1,
+	DSB2,
+	DSB3,
+	MAX_DSB_PER_PIPE
+};
+
+struct intel_dsb {
+	struct intel_crtc *crtc;
+	enum dsb_id id;
+	u32 *cmd_buf;
+	u32 cmd_buf_head;
+	struct i915_vma *vma;
+};
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc);
+
+#endif

Comments

On Mon, 12 Aug 2019, Animesh Manna <animesh.manna@intel.com> wrote:
> The function will internally get the gem buffer from global GTT
> which is mapped in cpu domain to feed the data + opcode for DSB engine.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |  1 +
>  .../drm/i915/display/intel_display_types.h    |  4 ++
>  drivers/gpu/drm/i915/i915_drv.h               |  1 +
>  drivers/gpu/drm/i915/intel_dsb.c              | 66 +++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dsb.h              | 31 +++++++++

This needs to move under display/ subdirectory. DSB is about display.

BR,
Jani.


>  5 files changed, 103 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/intel_dsb.c
>  create mode 100644 drivers/gpu/drm/i915/intel_dsb.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index d3ca46dc54ae..06458834fba7 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -50,6 +50,7 @@ i915-y += i915_drv.o \
>  	  i915_utils.o \
>  	  intel_csr.o \
>  	  intel_device_info.o \
> +	  intel_dsb.o \
>  	  intel_pch.o \
>  	  intel_pm.o \
>  	  intel_runtime_pm.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index a88ec9aa9ca0..56e91f04c9b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1025,6 +1025,10 @@ struct intel_crtc {
>  
>  	/* scalers available on this crtc */
>  	int num_scalers;
> +
> +	/* per pipe DSB related info */
> +	struct intel_dsb dsb[MAX_DSB_PER_PIPE];
> +	int dsb_in_use;
>  };
>  
>  struct intel_plane {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 29cb320fccf2..d8cf8ad94b30 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -81,6 +81,7 @@
>  #include "gt/uc/intel_uc.h"
>  
>  #include "intel_device_info.h"
> +#include "intel_dsb.h"
>  #include "intel_pch.h"
>  #include "intel_runtime_pm.h"
>  #include "intel_uncore.h"
> diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
> new file mode 100644
> index 000000000000..f404321ff665
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_dsb.c
> @@ -0,0 +1,66 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + */
> +
> +#include "i915_drv.h"
> +#include "display/intel_display_types.h"
> +
> +#define DSB_BUF_SIZE    (2 * PAGE_SIZE)
> +
> +struct intel_dsb *
> +intel_dsb_get(struct intel_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *i915 = to_i915(dev);
> +	struct drm_i915_gem_object *obj;
> +	struct i915_vma *vma;
> +	struct intel_dsb *dsb;
> +	intel_wakeref_t wakeref;
> +	int i;
> +
> +	WARN_ON(crtc->dsb_in_use >= MAX_DSB_PER_PIPE);
> +
> +	for (i = 0; i < MAX_DSB_PER_PIPE; i++) {
> +		if (!crtc->dsb[i].cmd_buf) {
> +			dsb = &crtc->dsb[i];
> +			dsb->id = i;
> +		}
> +	}
> +
> +	dsb = &crtc->dsb[crtc->dsb_in_use];
> +	dsb->crtc = crtc;
> +	if (!HAS_DSB(i915))
> +		return dsb;
> +
> +	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> +	mutex_lock(&i915->drm.struct_mutex);
> +
> +	obj = i915_gem_object_create_shmem(i915, DSB_BUF_SIZE);
> +	if (IS_ERR(obj))
> +		goto err;
> +
> +	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
> +	if (IS_ERR(vma)) {
> +		DRM_DEBUG_KMS("Vma creation failed.\n");
> +		i915_gem_object_put(obj);
> +		goto err;
> +	}
> +
> +	dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
> +	if (IS_ERR(dsb->cmd_buf)) {
> +		DRM_DEBUG_KMS("Command buffer creation failed.\n");
> +		dsb->cmd_buf = NULL;
> +		goto err;
> +	}
> +	crtc->dsb_in_use++;
> +	dsb->cmd_buf_head = (uintptr_t)i915_ggtt_offset(vma);
> +	dsb->vma = vma;
> +
> +	memset(dsb->cmd_buf, 0, DSB_BUF_SIZE);
> +err:
> +	mutex_unlock(&i915->drm.struct_mutex);
> +	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> +	return dsb;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_dsb.h b/drivers/gpu/drm/i915/intel_dsb.h
> new file mode 100644
> index 000000000000..50a2a6590a71
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_dsb.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#ifndef _INTEL_DSB_H
> +#define _INTEL_DSB_H
> +
> +struct intel_crtc;
> +struct i915_vma;
> +
> +enum dsb_id {
> +	INVALID_DSB = -1,
> +	DSB1,
> +	DSB2,
> +	DSB3,
> +	MAX_DSB_PER_PIPE
> +};
> +
> +struct intel_dsb {
> +	struct intel_crtc *crtc;
> +	enum dsb_id id;
> +	u32 *cmd_buf;
> +	u32 cmd_buf_head;
> +	struct i915_vma *vma;
> +};
> +
> +struct intel_dsb *
> +intel_dsb_get(struct intel_crtc *crtc);
> +
> +#endif