[2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus

Submitted by Kenneth Feng on Aug. 12, 2019, 5:24 a.m.

Details

Message ID MN2PR12MB3598346C347D13D3D16B52BB8ED30@MN2PR12MB3598.namprd12.prod.outlook.com
State New
Headers show
Series "Series without cover letter" ( rev: 7 6 5 4 ) in AMD X.Org drivers

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Commit Message

Kenneth Feng Aug. 12, 2019, 5:24 a.m.
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>



-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Le Ma

Sent: Friday, August 09, 2019 7:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le <Le.Ma@amd.com>
Subject: [PATCH 2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus

[CAUTION: External Email]

Follow the hw spec, and no need to consider gfxoff on Arcturus

Change-Id: Ib9cad79b1b9c096014447fc0a7d29cdb594e15e3
Signed-off-by: Le Ma <le.ma@amd.com>

---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

--
2.7.4

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diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 78150ff..9b85a73 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4677,8 +4677,12 @@  static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
                /* enable cgcg FSM(0x0000363F) */
                def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

-               data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
-                       RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+               if (adev->asic_type == CHIP_ARCTURUS)
+                       data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+                               RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+               else
+                       data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+                               RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
                        data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
                                RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;