[19/49] drm/amd/display: clean up DML for DCN2x

Submitted by sunpeng.li@amd.com on Aug. 9, 2019, 9:37 p.m.

Details

Message ID 20190809213742.30301-20-sunpeng.li@amd.com
State New
Headers show
Series "DC Patches 09 Aug, 2019" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

sunpeng.li@amd.com Aug. 9, 2019, 9:37 p.m.
From: Jun Lei <Jun.Lei@amd.com>

[why]
Previous "less risky" implemenation of 3 tiered fallback is no longer necessary since
DMLv2 has gone through proper validation.  v2 can now be used as the default and 1
level of fallback can be removed

[how]
remove previous workaround implemenation

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h           |  1 -
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 19 +++----------------
 2 files changed, 3 insertions(+), 17 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9824f5589a0b..2d3caa91d826 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -121,7 +121,6 @@  struct dc_caps {
 struct dc_bug_wa {
 	bool no_connect_phy_config;
 	bool dedcn20_305_wa;
-	struct display_mode_lib alternate_dml;
 	bool skip_clock_update;
 };
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 930ad54e0ff6..02a763321271 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2610,7 +2610,7 @@  bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
 		goto restore_dml_state;
 	}
 
-	// Fallback #1: Try to only support G6 temperature read latency
+	// Fallback: Try to only support G6 temperature read latency
 	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
 
 	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
@@ -2621,19 +2621,7 @@  bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
 		goto restore_dml_state;
 	}
 
-	// Fallback #2: Retry with "new" DCN20 to support G6 temperature read latency
-	memcpy (&context->bw_ctx.dml, &dc->work_arounds.alternate_dml, sizeof (struct display_mode_lib));
-	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
-
-	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
-	dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
-
-	if (voltage_supported && dummy_pstate_supported) {
-		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
-		goto restore_dml_state;
-	}
-
-	// ERROR: fallback #2 is supposed to always work.
+	// ERROR: fallback is supposed to always work.
 	ASSERT(false);
 
 restore_dml_state:
@@ -3238,8 +3226,7 @@  static bool construct(
 		goto create_fail;
 	}
 
-	dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10);
-	dml_init_instance(&dc->work_arounds.alternate_dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10v2);
+	dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10v2);
 
 	if (!dc->debug.disable_pplib_wm_range) {
 		struct pp_smu_wm_range_sets ranges = {0};