drm/amdgpu: use VCN firmware offset for cache window

Submitted by Liu, Leo on July 18, 2019, 3:49 p.m.

Details

Message ID 20190718154945.15004-1-leo.liu@amd.com
State New
Headers show
Series "drm/amdgpu/: use VCN firmware offset for cache window" ( rev: 2 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Liu, Leo July 18, 2019, 3:49 p.m.
Since we are using the signed FW now, and also using PSP firmware loading,
but it's still potential to break driver when loading FW directly
instead of PSP, so we should add offset.

Signed-off-by: Leo Liu <leo.liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ---
 1 file changed, 3 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 3cb62e448a37..88e3dedcf926 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -379,11 +379,8 @@  static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 			upper_32_bits(adev->vcn.inst->gpu_addr));
 		offset = size;
-		/* No signed header for now from firmware
 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
-		*/
-		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 	}
 
 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);

Comments

Am 18.07.19 um 17:49 schrieb Liu, Leo:
> Since we are using the signed FW now, and also using PSP firmware loading,
> but it's still potential to break driver when loading FW directly
> instead of PSP, so we should add offset.
>
> Signed-off-by: Leo Liu <leo.liu@amd.com>

Acked-by: Christian König <christian.koenig@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ---
>   1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 3cb62e448a37..88e3dedcf926 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -379,11 +379,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
>   		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>   			upper_32_bits(adev->vcn.inst->gpu_addr));
>   		offset = size;
> -		/* No signed header for now from firmware
>   		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
>   			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
> -		*/
> -		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
>   	}
>   
>   	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
> -----Original Message-----

> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of

> Christian K?nig

> Sent: Friday, July 19, 2019 3:33 PM

> To: Liu, Leo <Leo.Liu@amd.com>; amd-gfx@lists.freedesktop.org

> Subject: Re: [PATCH] drm/amdgpu: use VCN firmware offset for cache

> window

> 

> Am 18.07.19 um 17:49 schrieb Liu, Leo:

> > Since we are using the signed FW now, and also using PSP firmware

> > loading, but it's still potential to break driver when loading FW

> > directly instead of PSP, so we should add offset.

> >

> > Signed-off-by: Leo Liu <leo.liu@amd.com>

> 

> Acked-by: Christian König <christian.koenig@amd.com>


Thanks Leo!  

Patch is
Reviewed-by: Huang Rui <ray.huang@amd.com>


> 

> > ---

> >   drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ---

> >   1 file changed, 3 deletions(-)

> >

> > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

> > b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

> > index 3cb62e448a37..88e3dedcf926 100644

> > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

> > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

> > @@ -379,11 +379,8 @@ static void vcn_v2_0_mc_resume(struct

> amdgpu_device *adev)

> >   		WREG32_SOC15(UVD, 0,

> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

> >   			upper_32_bits(adev->vcn.inst->gpu_addr));

> >   		offset = size;

> > -		/* No signed header for now from firmware

> >   		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,

> >   			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);

> > -		*/

> > -		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,

> 0);

> >   	}

> >

> >   	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);

> 

> _______________________________________________

> amd-gfx mailing list

> amd-gfx@lists.freedesktop.org

> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> -----Original Message-----

> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Liu,

> Leo

> Sent: Thursday, July 18, 2019 11:50 PM

> To: amd-gfx@lists.freedesktop.org

> Cc: Liu, Leo <Leo.Liu@amd.com>

> Subject: [PATCH] drm/amdgpu: use VCN firmware offset for cache window

> 

> Since we are using the signed FW now, and also using PSP firmware loading,

> but it's still potential to break driver when loading FW directly instead of PSP,

> so we should add offset.

> 

> Signed-off-by: Leo Liu <leo.liu@amd.com>


Thanks Leo!
+ Aaron to give a test in our side.

Reviewed-by: Huang Rui <ray.huang@amd.com>


> ---

>  drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ---

>  1 file changed, 3 deletions(-)

> 

> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

> index 3cb62e448a37..88e3dedcf926 100644

> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

> @@ -379,11 +379,8 @@ static void vcn_v2_0_mc_resume(struct

> amdgpu_device *adev)

>  		WREG32_SOC15(UVD, 0,

> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

>  			upper_32_bits(adev->vcn.inst->gpu_addr));

>  		offset = size;

> -		/* No signed header for now from firmware

>  		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,

>  			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);

> -		*/

> -		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,

> 0);

>  	}

> 

>  	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);

> --

> 2.20.1

> 

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> amd-gfx@lists.freedesktop.org

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