drm/amdgpu/: use VCN firmware offset for cache window

Submitted by Liu, Leo on July 18, 2019, 3:46 p.m.

Details

Message ID 20190718154616.14841-1-leo.liu@amd.com
State Accepted
Commit 53ef3969ddb88a2ee0b69d37f60bd2b1f02f23c9
Headers show
Series "drm/amdgpu/: use VCN firmware offset for cache window" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Liu, Leo July 18, 2019, 3:46 p.m.
Since we are using the signed FW now, and also using PSP firmware loading,
but it's still potential to break driver when loading FW directly
instead of PSP, so we should add offset.

Signed-off-by: Leo Liu <leo.liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ---
 1 file changed, 3 deletions(-)

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diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 3cb62e448a37..88e3dedcf926 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -379,11 +379,8 @@  static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 			upper_32_bits(adev->vcn.inst->gpu_addr));
 		offset = size;
-		/* No signed header for now from firmware
 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
-		*/
-		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 	}
 
 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);