[3/3] drm/amd/powerplay: add mutex lock to protect dpm context resource

Submitted by Gui, Jack on July 18, 2019, 10:02 a.m.

Details

Message ID 1563444138-23948-3-git-send-email-Jack.Gui@amd.com
State New
Headers show
Series "Series without cover letter" ( rev: 2 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Gui, Jack July 18, 2019, 10:02 a.m.
add mutex lock to protect dpm context resource

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 5 +++--
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c     | 8 ++++++++
 3 files changed, 12 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 693414f..ac01960 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -664,6 +664,7 @@  static int smu_sw_init(void *handle)
 	smu->watermarks_bitmap = 0;
 	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 	smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+	mutex_init(&smu->smu_dpm.mutex);
 	smu->smu_dpm.default_sclk_limit = 0;
 	smu->smu_dpm.peak_sclk_limit = 0;
 
@@ -1471,9 +1472,9 @@  enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
 	if (!smu_dpm_ctx->dpm_context)
 		return -EINVAL;
 
-	mutex_lock(&(smu->mutex));
+	mutex_lock(&(smu_dpm_ctx->mutex));
 	level = smu_dpm_ctx->dpm_level;
-	mutex_unlock(&(smu->mutex));
+	mutex_unlock(&(smu_dpm_ctx->mutex));
 
 	return level;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index acb522b..b6fcad2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -449,6 +449,7 @@  struct smu_dpm_context {
 	struct smu_power_state *dpm_request_power_state;
 	struct smu_power_state *dpm_current_power_state;
 	struct mclock_latency_table *mclk_latency_table;
+	struct mutex mutex;
 };
 
 struct smu_power_gate {
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b4deb9e..2079097 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -693,7 +693,9 @@  static int navi10_force_clk_levels(struct smu_context *smu,
 	case SMU_GFXCLK:
 	case SMU_SCLK:
 		if (smu_dpm_ctx->peak_sclk_limit) {
+			mutex_lock(&smu_dpm_ctx->mutex);
 			max_freq = smu_dpm_ctx->peak_sclk_limit;
+			mutex_unlock(&smu_dpm_ctx->mutex);
 			ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 			if (ret)
 				return size;
@@ -878,7 +880,9 @@  static int navi10_unforce_dpm_levels(struct smu_context *smu)
 			return ret;
 
 		if (clk_type == SMU_GFXCLK && smu_dpm_ctx->default_sclk_limit != 0) {
+			mutex_lock(&smu_dpm_ctx->mutex);
 			max_freq = smu_dpm_ctx->default_sclk_limit;
+			mutex_unlock(&smu_dpm_ctx->mutex);
 			ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
 						     &min_freq, NULL);
 			if (ret)
@@ -888,7 +892,9 @@  static int navi10_unforce_dpm_levels(struct smu_context *smu)
 		if (ret)
 			return ret;
 	}
+	mutex_lock(&smu_dpm_ctx->mutex);
 	smu_dpm_ctx->peak_sclk_limit = 0;
+	mutex_unlock(&smu_dpm_ctx->mutex);
 
 	return ret;
 }
@@ -1571,6 +1577,7 @@  static int navi10_apply_clocks_adjust_rules(struct smu_context *smu)
 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 	struct amdgpu_device *adev = smu->adev;
 
+	mutex_lock(&smu_dpm_ctx->mutex);
 	if (smu_dpm_ctx->default_sclk_limit == 0) {
 		ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL,
 					     &smu_dpm_ctx->default_sclk_limit);
@@ -1588,6 +1595,7 @@  static int navi10_apply_clocks_adjust_rules(struct smu_context *smu)
 	} else if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && smu_dpm_ctx->peak_sclk_limit != 0) {
 		smu_dpm_ctx->peak_sclk_limit = 0;
 	}
+	mutex_unlock(&smu_dpm_ctx->mutex);
 
 	return 0;
 }