[2/4] radv: move emitting VGT_PRIMITIVEID_EN into the HW VS and NGG paths

Submitted by Samuel Pitoiset on July 17, 2019, 1:43 p.m.

Details

Message ID 20190717134353.5108-2-samuel.pitoiset@gmail.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Mesa

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Commit Message

Samuel Pitoiset July 17, 2019, 1:43 p.m.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
---
 src/amd/vulkan/radv_pipeline.c | 42 ++++++++++++----------------------
 1 file changed, 15 insertions(+), 27 deletions(-)

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diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 686fd371f0f..de933937f03 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3262,30 +3262,6 @@  radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
 			       S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
 }
 
-static void
-radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
-                                   struct radv_pipeline *pipeline)
-{
-	const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
-	const struct radv_shader_variant *vs =
-		pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
-		pipeline->shaders[MESA_SHADER_TESS_EVAL] :
-		pipeline->shaders[MESA_SHADER_VERTEX];
-	unsigned vgt_primitiveid_en = 0;
-
-	if (radv_pipeline_has_ngg(pipeline)) {
-		bool enable_prim_id =
-			outinfo->export_prim_id || vs->info.info.uses_prim_id;
-
-		vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(enable_prim_id) |
-				      S_028A84_NGG_DISABLE_PROVOK_REUSE(enable_prim_id);
-	} else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
-		vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
-	}
-
-	radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
-}
-
 static void
 gfx10_set_ge_pc_alloc(struct radeon_cmdbuf *ctx_cs,
 		      struct radv_pipeline *pipeline,
@@ -3368,7 +3344,7 @@  radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
 	 * GS and then back to the same GS used originally, the GS state is not
 	 * sent again.
 	 */
-	unsigned vgt_gs_mode;
+	unsigned vgt_primitiveid_en, vgt_gs_mode;
 	if (!radv_pipeline_has_gs(pipeline)) {
 		const struct radv_vs_output_info *outinfo =
 			get_vs_output_info(pipeline);
@@ -3376,22 +3352,27 @@  radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
 			pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
 			pipeline->shaders[MESA_SHADER_TESS_EVAL] :
 			pipeline->shaders[MESA_SHADER_VERTEX];
+		bool enable_prim_id = outinfo->export_prim_id ||
+				      vs->info.info.uses_prim_id;
 		unsigned mode = V_028A40_GS_OFF;
 
 		/* PrimID needs GS scenario A. */
-		if (outinfo->export_prim_id || vs->info.info.uses_prim_id)
+		if (enable_prim_id)
 			mode = V_028A40_GS_SCENARIO_A;
 
 		vgt_gs_mode = S_028A40_MODE(mode);
+		vgt_primitiveid_en = enable_prim_id;
 	} else {
 		const struct radv_shader_variant *gs =
 			pipeline->shaders[MESA_SHADER_GEOMETRY];
 
 		vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
 		                             pipeline->device->physical_device->rad_info.chip_class);
+		vgt_primitiveid_en = 0;
 	}
 
 	radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
+	radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
 
 	if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
 		radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
@@ -3448,6 +3429,8 @@  radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
 	uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 	gl_shader_stage es_type =
 		radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
+	struct radv_shader_variant *es =
+		es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
 
 	radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
 	radeon_emit(cs, va >> 8);
@@ -3464,6 +3447,8 @@  radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
 	bool misc_vec_ena = outinfo->writes_pointsize ||
 		outinfo->writes_layer ||
 		outinfo->writes_viewport_index;
+	bool es_enable_prim_id = outinfo->export_prim_id ||
+				 (es && es->info.info.uses_prim_id);
 	bool break_wave_at_eoi = false;
 	unsigned nparams;
 
@@ -3502,6 +3487,10 @@  radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
 	                       cull_dist_mask << 8 |
 	                       clip_dist_mask);
 
+	radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
+			       S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
+			       S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
+
 	bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 &&
 			     pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 &&
 			     es_type == MESA_SHADER_TESS_EVAL;
@@ -4065,7 +4054,6 @@  radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
 	radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
 	radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
 	radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
-	radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
 	radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess, ngg);
 	radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess, ngg);
 	radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs, ngg);