drm/amd/powerplay: enable fw ctf,apcc dfll and gfx ss

Submitted by Feng, Kenneth on July 16, 2019, 8:49 a.m.

Details

Message ID 1563266951-30106-1-git-send-email-kenneth.feng@amd.com
State Accepted
Commit 597292eb73eefe4e48f9f72640955813d59b733a
Headers show
Series "drm/amd/powerplay: enable fw ctf,apcc dfll and gfx ss" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Feng, Kenneth July 16, 2019, 8:49 a.m.
enable fw ctf, apcc dfll and gfx ss on navi10.
fw ctf: when the fw ctf is triggered, the gfx and soc power domain
are shut down. fan speed is boosted to the maximum.
gfx ss: hardware feature, sanity check has been done.
apcc dfll: can check the scoreboard in smu fw to confirm if it's enabled.
no need to do furhter check since the gfx hardware control the frquency once
a pcc signal comes.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e5..fa636d2 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -331,7 +331,10 @@  navi10_get_allowed_feature_mask(struct smu_context *smu,
 				| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 				| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 				| FEATURE_MASK(FEATURE_BACO_BIT)
-				| FEATURE_MASK(FEATURE_ACDC_BIT);
+				| FEATURE_MASK(FEATURE_ACDC_BIT)
+				| FEATURE_MASK(FEATURE_GFX_SS_BIT)
+				| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
+				| FEATURE_MASK(FEATURE_FW_CTF_BIT);
 
 	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
@@ -339,8 +342,7 @@  navi10_get_allowed_feature_mask(struct smu_context *smu,
 				| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 
 	if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
-		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
-				| FEATURE_MASK(FEATURE_GFXOFF_BIT);
+		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 		/* TODO: remove it once fw fix the bug */
 		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
 	}
@@ -465,9 +467,6 @@  static int navi10_append_powerplay_table(struct smu_context *smu)
 	smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 
 	if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
-		*(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
-					| FEATURE_MASK(FEATURE_GFXOFF_BIT);
-
 		/* TODO: remove it once SMU fw fix it */
 		smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 	}

Comments

Typo: furhter
With that fixed, the patch is Reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----

> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of

> Kenneth Feng

> Sent: Tuesday, July 16, 2019 4:49 PM

> To: amd-gfx@lists.freedesktop.org

> Cc: Feng, Kenneth <Kenneth.Feng@amd.com>

> Subject: [PATCH] drm/amd/powerplay: enable fw ctf,apcc dfll and gfx ss

> 

> enable fw ctf, apcc dfll and gfx ss on navi10.

> fw ctf: when the fw ctf is triggered, the gfx and soc power domain

> are shut down. fan speed is boosted to the maximum.

> gfx ss: hardware feature, sanity check has been done.

> apcc dfll: can check the scoreboard in smu fw to confirm if it's enabled.

> no need to do furhter check since the gfx hardware control the frquency

> once

> a pcc signal comes.

> 

> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>

> ---

>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 11 +++++------

>  1 file changed, 5 insertions(+), 6 deletions(-)

> 

> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c

> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c

> index 895a4e5..fa636d2 100644

> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c

> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c

> @@ -331,7 +331,10 @@ navi10_get_allowed_feature_mask(struct

> smu_context *smu,

>  				|

> FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)

>  				|

> FEATURE_MASK(FEATURE_FW_DSTATE_BIT)

>  				| FEATURE_MASK(FEATURE_BACO_BIT)

> -				| FEATURE_MASK(FEATURE_ACDC_BIT);

> +				| FEATURE_MASK(FEATURE_ACDC_BIT)

> +				| FEATURE_MASK(FEATURE_GFX_SS_BIT)

> +				| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)

> +				| FEATURE_MASK(FEATURE_FW_CTF_BIT);

> 

>  	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)

>  		*(uint64_t *)feature_mask |=

> FEATURE_MASK(FEATURE_DPM_UCLK_BIT)

> @@ -339,8 +342,7 @@ navi10_get_allowed_feature_mask(struct

> smu_context *smu,

>  				|

> FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);

> 

>  	if (adev->pm.pp_feature & PP_GFXOFF_MASK) {

> -		*(uint64_t *)feature_mask |=

> FEATURE_MASK(FEATURE_GFX_SS_BIT)

> -				| FEATURE_MASK(FEATURE_GFXOFF_BIT);

> +		*(uint64_t *)feature_mask |=

> FEATURE_MASK(FEATURE_GFXOFF_BIT);

>  		/* TODO: remove it once fw fix the bug */

>  		*(uint64_t *)feature_mask &=

> ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);

>  	}

> @@ -465,9 +467,6 @@ static int navi10_append_powerplay_table(struct

> smu_context *smu)

>  	smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;

> 

>  	if (adev->pm.pp_feature & PP_GFXOFF_MASK) {

> -		*(uint64_t *)smc_pptable->FeaturesToRun |=

> FEATURE_MASK(FEATURE_GFX_SS_BIT)

> -					|

> FEATURE_MASK(FEATURE_GFXOFF_BIT);

> -

>  		/* TODO: remove it once SMU fw fix it */

>  		smc_pptable->DebugOverrides |=

> DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;

>  	}

> --

> 2.7.4

> 

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