drm/dp/dsc: Add Support for all BPCs supported by TGL

Submitted by Srivatsa, Anusha on July 15, 2019, 11:40 p.m.

Details

Message ID 20190715234056.17112-1-anusha.srivatsa@intel.com
State New
Headers show
Series "drm/dp/dsc: Add Support for all BPCs supported by TGL" ( rev: 2 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Srivatsa, Anusha July 15, 2019, 11:40 p.m.
DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.

v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
and use the value directly.(More such defines can be removed
as part of future patches). (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0eb5d66f87a7..aa8bfb754fc1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1914,8 +1914,12 @@  static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
 		return -EINVAL;
 
-	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
-			    conn_state->max_requested_bpc);
+	/* Max DSC Input BPC for TGL+ is 12 */
+	if (INTEL_GEN(dev_priv) >= 12)
+		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
+	else
+		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
+				    conn_state->max_requested_bpc);
 
 	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
 	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {

Comments

On Mon, Jul 15, 2019 at 04:40:56PM -0700, Anusha Srivatsa wrote:
> DSC engine on ICL supports only 8 and 10 BPC as the input
> BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> Add 12 BPC support for DSC while calculating compression
> configuration.
> 
> v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
> and use the value directly.(More such defines can be removed
> as part of future patches). (Ville)

IMO what Ville asked to do in his comment was to remove all the #defines
for the max DSC BPC so remove the ones for 8 and 10 also to mak eit more readable
and that user does not have to hunt for the #defines for either of these.

> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0eb5d66f87a7..aa8bfb754fc1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>  		return -EINVAL;
>  
> -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> -			    conn_state->max_requested_bpc);
> +	/* Max DSC Input BPC for TGL+ is 12 */
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
> +	else
> +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> +				    conn_state->max_requested_bpc);

Use 10 here directly

>  
>  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {

Use 8 here directly

Manasi
> -- 
> 2.21.0
>
>-----Original Message-----
>From: Navare, Manasi D
>Sent: Tuesday, July 16, 2019 11:15 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä <ville.syrjala@linux.intel.com>
>Subject: Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
>
>On Mon, Jul 15, 2019 at 04:40:56PM -0700, Anusha Srivatsa wrote:
>> DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But DSC
>> engine in TGL supports 8, 10 and 12 BPC.
>> Add 12 BPC support for DSC while calculating compression
>> configuration.
>>
>> v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC and use
>> the value directly.(More such defines can be removed as part of future
>> patches). (Ville)
>
>IMO what Ville asked to do in his comment was to remove all the #defines for the
>max DSC BPC so remove the ones for 8 and 10 also to mak eit more readable and
>that user does not have to hunt for the #defines for either of these.

Yes those changes can be part of a following patch. This is TGL specific.

Anusha 
>>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
>>  1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 0eb5d66f87a7..aa8bfb754fc1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct
>intel_dp *intel_dp,
>>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>>  		return -EINVAL;
>>
>> -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> -			    conn_state->max_requested_bpc);
>> +	/* Max DSC Input BPC for TGL+ is 12 */
>> +	if (INTEL_GEN(dev_priv) >= 12)
>> +		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
>> +	else
>> +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> +				    conn_state->max_requested_bpc);
>
>Use 10 here directly
>
>>
>>  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>>  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
>
>Use 8 here directly
>
>Manasi
>> --
>> 2.21.0
>>
On Tue, Jul 16, 2019 at 01:26:19PM -0700, Srivatsa, Anusha wrote:
> 
> 
> >-----Original Message-----
> >From: Navare, Manasi D
> >Sent: Tuesday, July 16, 2019 11:15 AM
> >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> >Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä <ville.syrjala@linux.intel.com>
> >Subject: Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
> >
> >On Mon, Jul 15, 2019 at 04:40:56PM -0700, Anusha Srivatsa wrote:
> >> DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But DSC
> >> engine in TGL supports 8, 10 and 12 BPC.
> >> Add 12 BPC support for DSC while calculating compression
> >> configuration.
> >>
> >> v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC and use
> >> the value directly.(More such defines can be removed as part of future
> >> patches). (Ville)
> >
> >IMO what Ville asked to do in his comment was to remove all the #defines for the
> >max DSC BPC so remove the ones for 8 and 10 also to mak eit more readable and
> >that user does not have to hunt for the #defines for either of these.
> 
> Yes those changes can be part of a following patch. This is TGL specific.

IMO, you could just make them in the same patch since they are minor changes
happening because of diferent max limits for TGL, so just say in the commit message
while at it also remove the #defines and use the values directly for ICL limits as well.

Manasi

> 
> Anusha 
> >>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
> >>  1 file changed, 6 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index 0eb5d66f87a7..aa8bfb754fc1 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct
> >intel_dp *intel_dp,
> >>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> >>  		return -EINVAL;
> >>
> >> -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> -			    conn_state->max_requested_bpc);
> >> +	/* Max DSC Input BPC for TGL+ is 12 */
> >> +	if (INTEL_GEN(dev_priv) >= 12)
> >> +		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
> >> +	else
> >> +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> +				    conn_state->max_requested_bpc);
> >
> >Use 10 here directly
> >
> >>
> >>  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> >>  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> >
> >Use 8 here directly
> >
> >Manasi
> >> --
> >> 2.21.0
> >>