drm/amdgpu: drop copy/paste leftover to fix big endian

Submitted by Alex Deucher on June 27, 2019, 2:16 p.m.

Details

Message ID 20190627141628.7882-1-alexander.deucher@amd.com
State Accepted
Commit 687ac4a702ea92873fb8c45acec0c30eae9acfa9
Headers show
Series "drm/amdgpu: drop copy/paste leftover to fix big endian" ( rev: 1 ) in AMD X.Org drivers

Browsing this patch as part of:
"drm/amdgpu: drop copy/paste leftover to fix big endian" rev 1 in AMD X.Org drivers
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Commit Message

Alex Deucher June 27, 2019, 2:16 p.m.
The buf swap field doesn't exist on RB1.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ---
 1 file changed, 3 deletions(-)

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diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0061a0e8ab78..2932ade7dbd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -2624,9 +2624,6 @@  static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
 	rb_bufsz = order_base_2(ring->ring_size / 8);
 	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
 	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
-#ifdef __BIG_ENDIAN
-	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, BUF_SWAP, 1);
-#endif
 	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
 	/* Initialize the ring buffer's write pointers */
 	ring->wptr = 0;

Comments

On 2019-06-27 4:16 p.m., Alex Deucher wrote:
> The buf swap field doesn't exist on RB1.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 0061a0e8ab78..2932ade7dbd0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -2624,9 +2624,6 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
>  	rb_bufsz = order_base_2(ring->ring_size / 8);
>  	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
>  	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
> -#ifdef __BIG_ENDIAN
> -	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, BUF_SWAP, 1);
> -#endif
>  	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
>  	/* Initialize the ring buffer's write pointers */
>  	ring->wptr = 0;
> 

So the RB0 BUF_SWAP bit applies to RB1 as well? Might be nice to clarify
that in the commit log.

Anyway,

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
On Thu, Jun 27, 2019 at 10:32 AM Michel Dänzer <michel@daenzer.net> wrote:
>
> On 2019-06-27 4:16 p.m., Alex Deucher wrote:
> > The buf swap field doesn't exist on RB1.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ---
> >  1 file changed, 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 0061a0e8ab78..2932ade7dbd0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -2624,9 +2624,6 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
> >       rb_bufsz = order_base_2(ring->ring_size / 8);
> >       tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
> >       tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
> > -#ifdef __BIG_ENDIAN
> > -     tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, BUF_SWAP, 1);
> > -#endif
> >       WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
> >       /* Initialize the ring buffer's write pointers */
> >       ring->wptr = 0;
> >
>
> So the RB0 BUF_SWAP bit applies to RB1 as well? Might be nice to clarify
> that in the commit log.

Maybe?  I suspect there is no swapping on the other RB.  I'm not even
sure the swapping works on RB0, but the bits are still there.  Someone
would probably need to validate all of this on BE hardware.

Alex

>
> Anyway,
>
> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
>
>
> --
> Earthling Michel Dänzer               |              https://www.amd.com
> Libre software enthusiast             |             Mesa and X developer