drm/amd/display: update infoframe after dig fe is turned on (v2)

Submitted by Kazlauskas, Nicholas on June 24, 2019, 5:56 p.m.

Details

Message ID 20190624175631.25375-1-nicholas.kazlauskas@amd.com
State New
Headers show
Series "drm/amd/display: update infoframe after dig fe is turned on (v2)" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Kazlauskas, Nicholas June 24, 2019, 5:56 p.m.
[Why]
The AVI infoframe is incorrectly programmed on DCN1/2 when enabling a
stream - causing the wrong pixel encoding to be used for display.

This is because the AVI infoframe is programmed before the DIG BE is
connected to the FE and turned on, so enabling the AFMT block doesn't
actually work and the registers subsequently can't be written to.

[How]
Program the infoframe *after* turning on the DIG FE. This was the
behavior previously used but it was incorrectly reverted
when adding the DCN2 HW sequencer code.

Fixes: 54ff35915948 ("drm/amd/display: Add DCN2 HW Sequencer and Resource")

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Roman Li <roman.li@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 ++
 1 file changed, 2 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 940e74b7d2c6..b4b8ded16e22 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -666,6 +666,7 @@  void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 
 	/* update AVI info frame (HDMI, DP)*/
 	/* TODO: FPGA may change to hwss.update_info_frame */
+	dce110_update_info_frame(pipe_ctx);
 
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 	if (pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL &&
@@ -686,6 +687,7 @@  void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 							dmdata_dp : dmdata_hdmi);
 	}
 #endif
+	dce110_update_info_frame(pipe_ctx);
 
 	/* enable early control to avoid corruption on DP monitor*/
 	active_total_with_borders =