[1/2] radv: fix setting CB_DCC_BASE if the base level doesn't enable DCC

Submitted by Samuel Pitoiset on June 24, 2019, 3:03 p.m.

Details

Message ID 20190624150328.24031-1-samuel.pitoiset@gmail.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Mesa

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Commit Message

Samuel Pitoiset June 24, 2019, 3:03 p.m.
CB_DCC_BASE should be 0 if no DCC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
---
 src/amd/vulkan/radv_device.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

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diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 26b31cff9f1..dc5de683050 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4342,15 +4342,16 @@  radv_initialise_color_surface(struct radv_device *device,
 	va += iview->image->cmask.offset;
 	cb->cb_color_cmask = va >> 8;
 
-	va = radv_buffer_get_va(iview->bo) + iview->image->offset;
-	va += iview->image->dcc_offset;
+	if (radv_dcc_enabled(iview->image, iview->base_mip)) {
+		va = radv_buffer_get_va(iview->bo) + iview->image->offset;
+		va += iview->image->dcc_offset;
 
-	if (radv_dcc_enabled(iview->image, iview->base_mip) &&
-	    device->physical_device->rad_info.chip_class <= GFX8)
-		va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
+		if (device->physical_device->rad_info.chip_class <= GFX8)
+			va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
 
-	cb->cb_dcc_base = va >> 8;
-	cb->cb_dcc_base |= surf->tile_swizzle;
+		cb->cb_dcc_base = va >> 8;
+		cb->cb_dcc_base |= surf->tile_swizzle;
+	}
 
 	uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
 	cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |

Comments

why?

We should be regulating enabling it with S_028C70_DCC_ENABLE.

On Mon, Jun 24, 2019 at 5:00 PM Samuel Pitoiset
<samuel.pitoiset@gmail.com> wrote:
>
> CB_DCC_BASE should be 0 if no DCC.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
> ---
>  src/amd/vulkan/radv_device.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 26b31cff9f1..dc5de683050 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -4342,15 +4342,16 @@ radv_initialise_color_surface(struct radv_device *device,
>         va += iview->image->cmask.offset;
>         cb->cb_color_cmask = va >> 8;
>
> -       va = radv_buffer_get_va(iview->bo) + iview->image->offset;
> -       va += iview->image->dcc_offset;
> +       if (radv_dcc_enabled(iview->image, iview->base_mip)) {
> +               va = radv_buffer_get_va(iview->bo) + iview->image->offset;
> +               va += iview->image->dcc_offset;
>
> -       if (radv_dcc_enabled(iview->image, iview->base_mip) &&
> -           device->physical_device->rad_info.chip_class <= GFX8)
> -               va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
> +               if (device->physical_device->rad_info.chip_class <= GFX8)
> +                       va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
>
> -       cb->cb_dcc_base = va >> 8;
> -       cb->cb_dcc_base |= surf->tile_swizzle;
> +               cb->cb_dcc_base = va >> 8;
> +               cb->cb_dcc_base |= surf->tile_swizzle;
> +       }
>
>         uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
>         cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
> --
> 2.22.0
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
On 6/25/19 1:38 AM, Bas Nieuwenhuizen wrote:
> why?
>
> We should be regulating enabling it with S_028C70_DCC_ENABLE.
Correct. Please ignore this patch, it's not wrong, just useless.
>
> On Mon, Jun 24, 2019 at 5:00 PM Samuel Pitoiset
> <samuel.pitoiset@gmail.com> wrote:
>> CB_DCC_BASE should be 0 if no DCC.
>>
>> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
>> ---
>>   src/amd/vulkan/radv_device.c | 15 ++++++++-------
>>   1 file changed, 8 insertions(+), 7 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
>> index 26b31cff9f1..dc5de683050 100644
>> --- a/src/amd/vulkan/radv_device.c
>> +++ b/src/amd/vulkan/radv_device.c
>> @@ -4342,15 +4342,16 @@ radv_initialise_color_surface(struct radv_device *device,
>>          va += iview->image->cmask.offset;
>>          cb->cb_color_cmask = va >> 8;
>>
>> -       va = radv_buffer_get_va(iview->bo) + iview->image->offset;
>> -       va += iview->image->dcc_offset;
>> +       if (radv_dcc_enabled(iview->image, iview->base_mip)) {
>> +               va = radv_buffer_get_va(iview->bo) + iview->image->offset;
>> +               va += iview->image->dcc_offset;
>>
>> -       if (radv_dcc_enabled(iview->image, iview->base_mip) &&
>> -           device->physical_device->rad_info.chip_class <= GFX8)
>> -               va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
>> +               if (device->physical_device->rad_info.chip_class <= GFX8)
>> +                       va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
>>
>> -       cb->cb_dcc_base = va >> 8;
>> -       cb->cb_dcc_base |= surf->tile_swizzle;
>> +               cb->cb_dcc_base = va >> 8;
>> +               cb->cb_dcc_base |= surf->tile_swizzle;
>> +       }
>>
>>          uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
>>          cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
>> --
>> 2.22.0
>>
>> _______________________________________________
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev