drm/amdgpu: fix modprobe failure for uvd_4/5/6

Submitted by Tianci Yin on June 24, 2019, 12:08 p.m.

Details

Message ID MN2PR12MB2974DEB333EFC573700D0B5895E00@MN2PR12MB2974.namprd12.prod.outlook.com
State New
Headers show
Series "drm/amdgpu: fix modprobe failure for uvd_4/5/6" ( rev: 2 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Tianci Yin June 24, 2019, 12:08 p.m.
Reviewed-by: Tianci Yin <tianci.yin@amd.com>

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index f54a1ef..357e45f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -948,12 +948,21 @@  int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block

         switch (block_type) {
         case AMD_IP_BLOCK_TYPE_GFX:
+       case AMD_IP_BLOCK_TYPE_UVD:
+       case AMD_IP_BLOCK_TYPE_VCN:
+       case AMD_IP_BLOCK_TYPE_VCE:
                 if (swsmu)
-                       ret = smu_gfx_off_control(&adev->smu, gate);
+                       ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);
                 else
                         ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
                                 (adev)->powerplay.pp_handle, block_type, gate));
                 break;
+       case AMD_IP_BLOCK_TYPE_GMC:
+       case AMD_IP_BLOCK_TYPE_ACP:
+       case AMD_IP_BLOCK_TYPE_SDMA:
+               ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
+                               (adev)->powerplay.pp_handle, block_type, gate));
+               break;
         default:
                 break;
         }
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index edd1da6..f61ecbf 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -233,6 +233,9 @@  int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
         case AMD_IP_BLOCK_TYPE_VCE:
                 ret = smu_dpm_set_vce_enable(smu, gate);
                 break;
+       case AMD_IP_BLOCK_TYPE_GFX:
+               ret = smu_gfx_off_control(smu, gate);
+               break;
         default:
                 break;
         }