radeon/vcn: enable rate control for hevc encoding

Submitted by Zhang, Boyuan on June 17, 2019, 7:07 p.m.

Details

Message ID 20190617190727.21618-2-boyuan.zhang@amd.com
State New
Headers show
Series "radeon/uvd: enable rate control for hevc encoding" ( rev: 2 ) in Mesa

Not browsing as part of any series.

Commit Message

Zhang, Boyuan June 17, 2019, 7:07 p.m.
From: Boyuan Zhang <boyuan.zhang@amd.com>

Set cu_qp_delta_enable_flag on when rate control is enabled, and it
off when no rate control is disabled (constant qp).

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Patch hide | download patch | download mbox

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 3302ed7524..e4b9162034 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -687,7 +687,13 @@  static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
 	radeon_enc_code_se(enc, 0x0);
 	radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
 	radeon_enc_code_fixed_bits(enc, 0x0, 1);
-	radeon_enc_code_fixed_bits(enc, 0x0, 1);
+	if (enc->enc_pic.rc_session_init.rate_control_method ==
+		RENC_UVD_RATE_CONTROL_METHOD_NONE)
+		radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+	else {
+		radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
+		radeon_uvd_enc_code_ue(enc, 0x0);
+	}
 	radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 	radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 	radeon_enc_code_fixed_bits(enc, 0x0, 1);

Comments

Please tag the bugzilla link to the commit messages. With that, the set 
of patches are

Acked-by: Leo Liu <leo.liu@amd.com>



On 2019-06-17 3:07 p.m., boyuan.zhang@amd.com wrote:
> From: Boyuan Zhang <boyuan.zhang@amd.com>

>

> Set cu_qp_delta_enable_flag on when rate control is enabled, and it

> off when no rate control is disabled (constant qp).

>

> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>

> ---

>   src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 8 +++++++-

>   1 file changed, 7 insertions(+), 1 deletion(-)

>

> diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c

> index 3302ed7524..e4b9162034 100644

> --- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c

> +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c

> @@ -687,7 +687,13 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)

>   	radeon_enc_code_se(enc, 0x0);

>   	radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);

>   	radeon_enc_code_fixed_bits(enc, 0x0, 1);

> -	radeon_enc_code_fixed_bits(enc, 0x0, 1);

> +	if (enc->enc_pic.rc_session_init.rate_control_method ==

> +		RENC_UVD_RATE_CONTROL_METHOD_NONE)

> +		radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);

> +	else {

> +		radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);

> +		radeon_uvd_enc_code_ue(enc, 0x0);

> +	}

>   	radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);

>   	radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);

>   	radeon_enc_code_fixed_bits(enc, 0x0, 1);