[3/6] panfrost: Control texop value earlier

Submitted by Boris Brezillon on June 17, 2019, 2:54 p.m.

Details

Message ID 20190617165419.051a4794@collabora.com
State New
Headers show
Series "panfrost: Add support for TXS instructions" ( rev: 2 ) in Mesa

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Commit Message

Boris Brezillon June 17, 2019, 2:54 p.m.
On Mon, 17 Jun 2019 07:09:16 -0700
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> wrote:

> > No problem, I'll rebase once this work has landed.  
> 
> I thought it has?

Then it's all good (I'm based on mesa master from today, and just
fetched/rebased 2 minutes ago to make sure I had everything).

> 
> > Hm, the list of allowed ops is likely to differ (doesn't make sense to
> > allow txs instructions when building a midgard tex instruction) so I'm
> > not sure it's a good idea to share this switch statement.  
> 
> Well, I was maybe more suggesting the switch statement up there would
> return NULL/false/-1/whatever for a NIR op not representable by a
> (single) Midgard tex instruction. So we call for the op at the
> beginning, and based on the results choose between two different
> funciton calls (one for a Midgard tex op, one for special handling).

Okay. How about something like the below diff?

> 
> Not sure, just wondering :)

Thanks for the review!

Boris

--->8---

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diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index a887c4dcd911..6e81cb46cd63 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1360,38 +1360,22 @@  midgard_tex_format(enum glsl_sampler_dim dim)
         }
 }
 
-static unsigned
-midgard_tex_op(nir_texop op)
-{
-        switch (op) {
-                case nir_texop_tex:
-                case nir_texop_txb:
-                        return TEXTURE_OP_NORMAL;
-                case nir_texop_txl:
-                        return TEXTURE_OP_LOD;
-                default:
-                        unreachable("Unhanlded texture op");
-        }
-}
+struct midgard_texop_desc;
+
+struct midgard_texop_desc {
+       unsigned mid;
+       void (*handler)(compiler_context *ctx,
+                       nir_tex_instr *instr,
+                       const struct midgard_texop_desc *mdesc);
+};
 
 static void
-emit_tex(compiler_context *ctx, nir_tex_instr *instr)
+emit_texop_tex_txb_txl(compiler_context *ctx, nir_tex_instr *instr,
+                       const struct midgard_texop_desc *mdesc)
 {
         /* TODO */
         //assert (!instr->sampler);
         //assert (!instr->texture_array_size);
-        switch (instr->op) {
-        case nir_texop_txs:
-                emit_sysval_read(ctx, &instr->instr);
-                return;
-        case nir_texop_tex:
-        case nir_texop_txb:
-        case nir_texop_txl:
-                break;
-        default:
-                unreachable("Unhanlded texture op");
-        }
-
         /* Allocate registers via a round robin scheme to alternate between the two registers */
         int reg = ctx->texture_op_count & 1;
         int in_reg = reg, out_reg = reg;
@@ -1461,7 +1445,7 @@  emit_tex(compiler_context *ctx, nir_tex_instr *instr)
         midgard_instruction ins = {
                 .type = TAG_TEXTURE_4,
                 .texture = {
-                        .op = midgard_tex_op(instr->op),
+                        .op = mdesc->mid,
                         .format = midgard_tex_format(instr->sampler_dim),
                         .texture_handle = texture_index,
                         .sampler_handle = sampler_index,
@@ -1519,6 +1503,50 @@  emit_tex(compiler_context *ctx, nir_tex_instr *instr)
         ctx->texture_op_count++;
 }
 
+static void
+emit_texop_txs(compiler_context *ctx, nir_tex_instr *instr,
+         const struct midgard_texop_desc *mdesc)
+{
+        emit_sysval_read(ctx, &instr->instr);
+}
+
+static const struct midgard_texop_desc midgard_texops[] = {
+       [nir_texop_tex] = {
+               .mid = TEXTURE_OP_NORMAL,
+               .handler = emit_texop_tex_txb_txl,
+       },
+       [nir_texop_txb] = {
+               .mid = TEXTURE_OP_NORMAL,
+               .handler = emit_texop_tex_txb_txl,
+       },
+       [nir_texop_txl] = {
+               .mid = TEXTURE_OP_LOD,
+               .handler = emit_texop_tex_txb_txl,
+       },
+       [nir_texop_txs] = {
+               .handler = emit_texop_txs,
+       },
+};
+
+static const struct midgard_texop_desc *
+midgard_get_texop_desc(nir_texop op)
+{
+       if (op < ARRAY_SIZE(midgard_texops) &&
+            midgard_texops[op].handler)
+                return &midgard_texops[op];
+
+       return NULL;
+}
+
+static void
+emit_tex(compiler_context *ctx, nir_tex_instr *instr)
+{
+        const struct midgard_texop_desc *mdesc = midgard_get_texop_desc(instr->op);
+
+        assert(mdesc);
+       mdesc->handler(ctx, instr, mdesc);
+}
+
 static void
 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
 {