[3/6] panfrost: Control texop value earlier

Submitted by Boris Brezillon on June 17, 2019, 10:49 a.m.


Message ID 20190617104928.24007-4-boris.brezillon@collabora.com
State New
Headers show
Series "panfrost: Add support for TXS instructions" ( rev: 1 ) in Mesa

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Commit Message

Boris Brezillon June 17, 2019, 10:49 a.m.
Right now the failure happens when building the midgard texture
instruction. Since we're about to add support for texop_txs (texture
size) which is does not involve the creation of a texture instruction,
let's add a instr->op check at the beginning of the emit_tex() function
so we can easily branch to a different path when needed.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
 src/gallium/drivers/panfrost/midgard/midgard_compile.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Patch hide | download patch | download mbox

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 1374c1ee6475..28aad38cc984 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1333,6 +1333,14 @@  emit_tex(compiler_context *ctx, nir_tex_instr *instr)
         /* TODO */
         //assert (!instr->sampler);
         //assert (!instr->texture_array_size);
+        switch (instr->op) {
+        case nir_texop_tex:
+        case nir_texop_txb:
+        case nir_texop_txl:
+                break;
+        default:
+                unreachable("Unhanlded texture op");
+        }
         /* Allocate registers via a round robin scheme to alternate between the two registers */
         int reg = ctx->texture_op_count & 1;


On Mon, 17 Jun 2019 06:56:11 -0700
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> wrote:

> This conflicts with texture bias/LOD work (in a functional sense, not
> a git sense).

No problem, I'll rebase once this work has landed.

> We can probably reuse the switch from the previous
> function rather than duplicating the op list :)

Hm, the list of allowed ops is likely to differ (doesn't make sense to
allow txs instructions when building a midgard tex instruction) so I'm
not sure it's a good idea to share this switch statement.