iris/ehl: disable repacking for compression for compatibilty

Submitted by Dongwon Kim on June 4, 2019, 4:14 p.m.

Details

Message ID 20190604161459.31818-1-dongwon.kim@intel.com
State New
Headers show
Series "iris/ehl: disable repacking for compression for compatibilty" ( rev: 1 ) in Mesa

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Commit Message

Dongwon Kim June 4, 2019, 4:14 p.m.
Repacking components in certain pixel formats before compression
shouldn't be done for EHL to keep the compatibility with decompression
capability in its display controller.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
---
 src/gallium/drivers/iris/iris_state.c | 10 +++++++++
 src/intel/dev/gen_device_info.c       |  4 ++++
 src/intel/dev/gen_device_info.h       |  1 +
 src/intel/genxml/gen11.xml            | 30 +++++++++++++--------------
 4 files changed, 29 insertions(+), 16 deletions(-)

Patch hide | download patch | download mbox

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index fb72c4b5b7d..cc9e1148418 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -749,6 +749,16 @@  iris_init_render_context(struct iris_screen *screen,
       }
       iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val);
 
+      /* needed to disable replacking to keep the compatibility with
+       * decompressing mechanism in display controller.
+       */
+      if (devinfo->need_disable_ccs_repack) {
+         iris_pack_state(GENX(CACHE_MODE_0), &reg_val, reg) {
+            reg.DisableRepackingforCompression = true;
+            reg.DisableRepackingforCompressionMask = true;
+         }
+         iris_emit_lri(batch, CACHE_MODE_0, reg_val);
+      }
 
       // XXX: 3D_MODE?
 #endif
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index fec6159fd37..ee3ad7ba085 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -64,6 +64,7 @@  gen_device_name_to_pci_device_id(const char *name)
       { "cml", 0x9b41 },
       { "cnl", 0x5a52 },
       { "icl", 0x8a52 },
+      { "ehl", 0x4500 },
    };
 
    for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
@@ -958,6 +959,7 @@  static const struct gen_device_info gen_device_info_ehl_4x8 = {
          [MESA_SHADER_GEOMETRY]  = 1032,
       },
    },
+   .need_disable_ccs_repack = 1,
    .simulator_id = 28,
 };
 
@@ -978,6 +980,7 @@  static const struct gen_device_info gen_device_info_ehl_4x4 = {
          [MESA_SHADER_GEOMETRY]  = 1032,
       },
    },
+   .need_disable_ccs_repack = 1,
    .num_eu_per_subslice = 4,
    .simulator_id = 28,
 };
@@ -999,6 +1002,7 @@  static const struct gen_device_info gen_device_info_ehl_2x4 = {
          [MESA_SHADER_GEOMETRY]  = 1032,
       },
    },
+   .need_disable_ccs_repack = 1,
    .num_eu_per_subslice =4,
    .simulator_id = 28,
 };
diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
index af13615be2b..e90d31935f1 100644
--- a/src/intel/dev/gen_device_info.h
+++ b/src/intel/dev/gen_device_info.h
@@ -74,6 +74,7 @@  struct gen_device_info
    bool has_surface_tile_offset;
    bool supports_simd16_3src;
    bool has_resource_streamer;
+   bool need_disable_ccs_repack;
 
    /**
     * \name Intel hardware quirks
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 1579345f69f..c1774501f4c 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -6818,30 +6818,28 @@ 
   </register>
 
   <register name="CACHE_MODE_0" length="1" num="0x7000">
-    <field name="Null tile fix disable" start="0" end="0" type="bool"/>
+    <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp" start="0" end="0" type="bool"/>
     <field name="Disable clock gating in the pixel backend" start="1" end="1" type="bool"/>
-    <field name="Hierarchical Z RAW Stall Optimization Disable" start="2" end="2" type="bool"/>
+    <field name="Hierarchical Z Disable" start="3" end="3" type="bool"/>
     <field name="RCC Eviction Policy" start="4" end="4" type="bool"/>
-    <field name="STC PMA Optimization Enable" start="5" end="5" type="bool"/>
-    <field name="Sampler L2 Request Arbitration" start="6" end="7" type="uint">
-      <value name="Round Robin" value="0"/>
-      <value name="Fetch are Highest Priority" value="1"/>
-      <value name="Constants are Highest Priority" value="2"/>
-    </field>
+    <field name="STC PMA Optimization Disable" start="5" end="5" type="bool"/>
+    <field name="STC Read-Hit Wonly Optimization Disable" start="6" end="6" type="bool"/>
+    <field name="Depth Related Cache Pipelined Flush Disable" start="8" end="8" type="bool"/>
     <field name="Sampler L2 TLB Prefetch Enable" start="9" end="9" type="bool"/>
-    <field name="Sampler Set Remapping for 3D Disable" start="11" end="11" type="bool"/>
+    <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters" start="10" end="10" type="bool"/>
     <field name="MSAA Compression Plane Number Threshold for eLLC" start="12" end="14" type="uint"/>
-    <field name="Sampler L2 Disable" start="15" end="15" type="bool"/>
-    <field name="Null tile fix disable Mask" start="16" end="16" type="bool"/>
+    <field name="Disable Repacking for Compression" start="15" end="15" type="bool"/>
+    <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp Mask" start="16" end="16" type="bool"/>
     <field name="Disable clock gating in the pixel backend Mask" start="17" end="17" type="bool"/>
-    <field name="Hierarchical Z RAW Stall Optimization Disable Mask" start="18" end="18" type="bool"/>
+    <field name="Hierarchical Z Disable Mask" start="19" end="19" type="bool"/>
     <field name="RCC Eviction Policy Mask" start="20" end="20" type="bool"/>
-    <field name="STC PMA Optimization Enable Mask" start="21" end="21" type="bool"/>
-    <field name="Sampler L2 Request Arbitration Mask" start="22" end="23" type="uint"/>
+    <field name="STC PMA Optimization Disable Mask" start="21" end="21" type="bool"/>
+    <field name="STC Read-Hit Wonly Optimization Disable Mask" start="22" end="22" type="bool"/>
+    <field name="Depth Related Cache Pipelined Flush Disable Mask" start="24" end="24" type="bool"/>
     <field name="Sampler L2 TLB Prefetch Enable Mask" start="25" end="25" type="bool"/>
-    <field name="Sampler Set Remapping for 3D Disable Mask" start="27" end="27" type="bool"/>
+    <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters Mask" start="26" end="26" type="bool"/>
     <field name="MSAA Compression Plane Number Threshold for eLLC Mask" start="28" end="30" type="uint"/>
-    <field name="Sampler L2 Disable Mask" start="31" end="31" type="bool"/>
+    <field name="Disable Repacking for Compression Mask" start="31" end="31" type="bool"/>
   </register>
 
   <register name="CACHE_MODE_1" length="1" num="0x7004">

Comments

On Tue, Jun 4, 2019 at 9:20 AM Dongwon Kim <dongwon.kim@intel.com> wrote:
>
> Repacking components in certain pixel formats before compression
> shouldn't be done for EHL to keep the compatibility with decompression
> capability in its display controller.
>
> Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
> ---
>  src/gallium/drivers/iris/iris_state.c | 10 +++++++++
>  src/intel/dev/gen_device_info.c       |  4 ++++
>  src/intel/dev/gen_device_info.h       |  1 +
>  src/intel/genxml/gen11.xml            | 30 +++++++++++++--------------
>  4 files changed, 29 insertions(+), 16 deletions(-)
>
> diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
> index fb72c4b5b7d..cc9e1148418 100644
> --- a/src/gallium/drivers/iris/iris_state.c
> +++ b/src/gallium/drivers/iris/iris_state.c
> @@ -749,6 +749,16 @@ iris_init_render_context(struct iris_screen *screen,
>        }
>        iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val);
>
> +      /* needed to disable replacking to keep the compatibility with
Hardware specification recommends disabling repacking ....
> +       * decompressing mechanism in display controller.
decompression ...
> +       */
> +      if (devinfo->need_disable_ccs_repack) {
> +         iris_pack_state(GENX(CACHE_MODE_0), &reg_val, reg) {
> +            reg.DisableRepackingforCompression = true;
> +            reg.DisableRepackingforCompressionMask = true;
> +         }
> +         iris_emit_lri(batch, CACHE_MODE_0, reg_val);
> +      }
>
>        // XXX: 3D_MODE?
>  #endif
> diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
> index fec6159fd37..ee3ad7ba085 100644
> --- a/src/intel/dev/gen_device_info.c
> +++ b/src/intel/dev/gen_device_info.c
> @@ -64,6 +64,7 @@ gen_device_name_to_pci_device_id(const char *name)
>        { "cml", 0x9b41 },
>        { "cnl", 0x5a52 },
>        { "icl", 0x8a52 },
> +      { "ehl", 0x4500 },
>     };
>
>     for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
> @@ -958,6 +959,7 @@ static const struct gen_device_info gen_device_info_ehl_4x8 = {
>           [MESA_SHADER_GEOMETRY]  = 1032,
>        },
>     },
> +   .need_disable_ccs_repack = 1,
>     .simulator_id = 28,
>  };
>
> @@ -978,6 +980,7 @@ static const struct gen_device_info gen_device_info_ehl_4x4 = {
>           [MESA_SHADER_GEOMETRY]  = 1032,
>        },
>     },
> +   .need_disable_ccs_repack = 1,
>     .num_eu_per_subslice = 4,
>     .simulator_id = 28,
>  };
> @@ -999,6 +1002,7 @@ static const struct gen_device_info gen_device_info_ehl_2x4 = {
>           [MESA_SHADER_GEOMETRY]  = 1032,
>        },
>     },
> +   .need_disable_ccs_repack = 1,
>     .num_eu_per_subslice =4,
>     .simulator_id = 28,
>  };
> diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
> index af13615be2b..e90d31935f1 100644
> --- a/src/intel/dev/gen_device_info.h
> +++ b/src/intel/dev/gen_device_info.h
> @@ -74,6 +74,7 @@ struct gen_device_info
>     bool has_surface_tile_offset;
>     bool supports_simd16_3src;
>     bool has_resource_streamer;
> +   bool need_disable_ccs_repack;
How about disable_ccs_repack ?
>
>     /**
>      * \name Intel hardware quirks
> diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
> index 1579345f69f..c1774501f4c 100644
> --- a/src/intel/genxml/gen11.xml
> +++ b/src/intel/genxml/gen11.xml
> @@ -6818,30 +6818,28 @@
>    </register>
>
>    <register name="CACHE_MODE_0" length="1" num="0x7000">
> -    <field name="Null tile fix disable" start="0" end="0" type="bool"/>
> +    <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp" start="0" end="0" type="bool"/>
>      <field name="Disable clock gating in the pixel backend" start="1" end="1" type="bool"/>
> -    <field name="Hierarchical Z RAW Stall Optimization Disable" start="2" end="2" type="bool"/>
> +    <field name="Hierarchical Z Disable" start="3" end="3" type="bool"/>
>      <field name="RCC Eviction Policy" start="4" end="4" type="bool"/>
> -    <field name="STC PMA Optimization Enable" start="5" end="5" type="bool"/>
> -    <field name="Sampler L2 Request Arbitration" start="6" end="7" type="uint">
> -      <value name="Round Robin" value="0"/>
> -      <value name="Fetch are Highest Priority" value="1"/>
> -      <value name="Constants are Highest Priority" value="2"/>
> -    </field>
> +    <field name="STC PMA Optimization Disable" start="5" end="5" type="bool"/>
> +    <field name="STC Read-Hit Wonly Optimization Disable" start="6" end="6" type="bool"/>
> +    <field name="Depth Related Cache Pipelined Flush Disable" start="8" end="8" type="bool"/>
>      <field name="Sampler L2 TLB Prefetch Enable" start="9" end="9" type="bool"/>
> -    <field name="Sampler Set Remapping for 3D Disable" start="11" end="11" type="bool"/>
> +    <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters" start="10" end="10" type="bool"/>
>      <field name="MSAA Compression Plane Number Threshold for eLLC" start="12" end="14" type="uint"/>
> -    <field name="Sampler L2 Disable" start="15" end="15" type="bool"/>
> -    <field name="Null tile fix disable Mask" start="16" end="16" type="bool"/>
> +    <field name="Disable Repacking for Compression" start="15" end="15" type="bool"/>
> +    <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp Mask" start="16" end="16" type="bool"/>
>      <field name="Disable clock gating in the pixel backend Mask" start="17" end="17" type="bool"/>
> -    <field name="Hierarchical Z RAW Stall Optimization Disable Mask" start="18" end="18" type="bool"/>
> +    <field name="Hierarchical Z Disable Mask" start="19" end="19" type="bool"/>
>      <field name="RCC Eviction Policy Mask" start="20" end="20" type="bool"/>
> -    <field name="STC PMA Optimization Enable Mask" start="21" end="21" type="bool"/>
> -    <field name="Sampler L2 Request Arbitration Mask" start="22" end="23" type="uint"/>
> +    <field name="STC PMA Optimization Disable Mask" start="21" end="21" type="bool"/>
> +    <field name="STC Read-Hit Wonly Optimization Disable Mask" start="22" end="22" type="bool"/>
> +    <field name="Depth Related Cache Pipelined Flush Disable Mask" start="24" end="24" type="bool"/>
>      <field name="Sampler L2 TLB Prefetch Enable Mask" start="25" end="25" type="bool"/>
> -    <field name="Sampler Set Remapping for 3D Disable Mask" start="27" end="27" type="bool"/>
> +    <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters Mask" start="26" end="26" type="bool"/>
>      <field name="MSAA Compression Plane Number Threshold for eLLC Mask" start="28" end="30" type="uint"/>
> -    <field name="Sampler L2 Disable Mask" start="31" end="31" type="bool"/>
> +    <field name="Disable Repacking for Compression Mask" start="31" end="31" type="bool"/>
>    </register>
I would recommend to pull out all above changes where you're
fixing  fields of CACHE_MODE_0 in a separate patch.
>
>    <register name="CACHE_MODE_1" length="1" num="0x7004">
> --
> 2.17.1
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
+mesa-dev

On Thu, Jun 20, 2019 at 12:20 PM Anuj Phogat <anuj.phogat@gmail.com> wrote:
>
> I sent out comments on your older patch. They applies to this patch too.
> Split i965 and anv changes in separate patches.
>
> On Thu, Jun 20, 2019 at 11:25 AM Dongwon Kim <dongwon.kim@intel.com> wrote:
> >
> > Repacking components in certain pixel formats before compression
> > shouldn't be done for EHL to keep the compatibility with decompression
> > capability in its display controller.
> >
> > v2: applied to iris, i965 and anvil.
> >
> > Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
> > ---
> >  src/gallium/drivers/iris/iris_state.c        | 10 +++++++
> >  src/intel/dev/gen_device_info.c              |  4 +++
> >  src/intel/dev/gen_device_info.h              |  1 +
> >  src/intel/genxml/gen11.xml                   | 30 +++++++++-----------
> >  src/intel/vulkan/genX_state.c                | 18 ++++++++++++
> >  src/mesa/drivers/dri/i965/brw_defines.h      |  1 +
> >  src/mesa/drivers/dri/i965/brw_state_upload.c |  9 ++++++
> >  7 files changed, 57 insertions(+), 16 deletions(-)
> >
> > diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
> > index 23f8d290368..8744178e94d 100644
> > --- a/src/gallium/drivers/iris/iris_state.c
> > +++ b/src/gallium/drivers/iris/iris_state.c
> > @@ -749,6 +749,16 @@ iris_init_render_context(struct iris_screen *screen,
> >        }
> >        iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val);
> >
> > +      /* needed to disable replacking to keep the compatibility with
> > +       * decompressing mechanism in display controller.
> > +       */
> > +      if (devinfo->need_disable_ccs_repack) {
> > +         iris_pack_state(GENX(CACHE_MODE_0), &reg_val, reg) {
> > +            reg.DisableRepackingforCompression = true;
> > +            reg.DisableRepackingforCompressionMask = true;
> > +         }
> > +         iris_emit_lri(batch, CACHE_MODE_0, reg_val);
> > +      }
> >
> >        // XXX: 3D_MODE?
> >  #endif
> > diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
> > index fec6159fd37..ee3ad7ba085 100644
> > --- a/src/intel/dev/gen_device_info.c
> > +++ b/src/intel/dev/gen_device_info.c
> > @@ -64,6 +64,7 @@ gen_device_name_to_pci_device_id(const char *name)
> >        { "cml", 0x9b41 },
> >        { "cnl", 0x5a52 },
> >        { "icl", 0x8a52 },
> > +      { "ehl", 0x4500 },
> >     };
> >
> >     for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
> > @@ -958,6 +959,7 @@ static const struct gen_device_info gen_device_info_ehl_4x8 = {
> >           [MESA_SHADER_GEOMETRY]  = 1032,
> >        },
> >     },
> > +   .need_disable_ccs_repack = 1,
> >     .simulator_id = 28,
> >  };
> >
> > @@ -978,6 +980,7 @@ static const struct gen_device_info gen_device_info_ehl_4x4 = {
> >           [MESA_SHADER_GEOMETRY]  = 1032,
> >        },
> >     },
> > +   .need_disable_ccs_repack = 1,
> >     .num_eu_per_subslice = 4,
> >     .simulator_id = 28,
> >  };
> > @@ -999,6 +1002,7 @@ static const struct gen_device_info gen_device_info_ehl_2x4 = {
> >           [MESA_SHADER_GEOMETRY]  = 1032,
> >        },
> >     },
> > +   .need_disable_ccs_repack = 1,
> >     .num_eu_per_subslice =4,
> >     .simulator_id = 28,
> >  };
> > diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
> > index af13615be2b..e90d31935f1 100644
> > --- a/src/intel/dev/gen_device_info.h
> > +++ b/src/intel/dev/gen_device_info.h
> > @@ -74,6 +74,7 @@ struct gen_device_info
> >     bool has_surface_tile_offset;
> >     bool supports_simd16_3src;
> >     bool has_resource_streamer;
> > +   bool need_disable_ccs_repack;
> >
> >     /**
> >      * \name Intel hardware quirks
> > diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
> > index 1579345f69f..c1774501f4c 100644
> > --- a/src/intel/genxml/gen11.xml
> > +++ b/src/intel/genxml/gen11.xml
> > @@ -6818,30 +6818,28 @@
> >    </register>
> >
> >    <register name="CACHE_MODE_0" length="1" num="0x7000">
> > -    <field name="Null tile fix disable" start="0" end="0" type="bool"/>
> > +    <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp" start="0" end="0" type="bool"/>
> >      <field name="Disable clock gating in the pixel backend" start="1" end="1" type="bool"/>
> > -    <field name="Hierarchical Z RAW Stall Optimization Disable" start="2" end="2" type="bool"/>
> > +    <field name="Hierarchical Z Disable" start="3" end="3" type="bool"/>
> >      <field name="RCC Eviction Policy" start="4" end="4" type="bool"/>
> > -    <field name="STC PMA Optimization Enable" start="5" end="5" type="bool"/>
> > -    <field name="Sampler L2 Request Arbitration" start="6" end="7" type="uint">
> > -      <value name="Round Robin" value="0"/>
> > -      <value name="Fetch are Highest Priority" value="1"/>
> > -      <value name="Constants are Highest Priority" value="2"/>
> > -    </field>
> > +    <field name="STC PMA Optimization Disable" start="5" end="5" type="bool"/>
> > +    <field name="STC Read-Hit Wonly Optimization Disable" start="6" end="6" type="bool"/>
> > +    <field name="Depth Related Cache Pipelined Flush Disable" start="8" end="8" type="bool"/>
> >      <field name="Sampler L2 TLB Prefetch Enable" start="9" end="9" type="bool"/>
> > -    <field name="Sampler Set Remapping for 3D Disable" start="11" end="11" type="bool"/>
> > +    <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters" start="10" end="10" type="bool"/>
> >      <field name="MSAA Compression Plane Number Threshold for eLLC" start="12" end="14" type="uint"/>
> > -    <field name="Sampler L2 Disable" start="15" end="15" type="bool"/>
> > -    <field name="Null tile fix disable Mask" start="16" end="16" type="bool"/>
> > +    <field name="Disable Repacking for Compression" start="15" end="15" type="bool"/>
> > +    <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp Mask" start="16" end="16" type="bool"/>
> >      <field name="Disable clock gating in the pixel backend Mask" start="17" end="17" type="bool"/>
> > -    <field name="Hierarchical Z RAW Stall Optimization Disable Mask" start="18" end="18" type="bool"/>
> > +    <field name="Hierarchical Z Disable Mask" start="19" end="19" type="bool"/>
> >      <field name="RCC Eviction Policy Mask" start="20" end="20" type="bool"/>
> > -    <field name="STC PMA Optimization Enable Mask" start="21" end="21" type="bool"/>
> > -    <field name="Sampler L2 Request Arbitration Mask" start="22" end="23" type="uint"/>
> > +    <field name="STC PMA Optimization Disable Mask" start="21" end="21" type="bool"/>
> > +    <field name="STC Read-Hit Wonly Optimization Disable Mask" start="22" end="22" type="bool"/>
> > +    <field name="Depth Related Cache Pipelined Flush Disable Mask" start="24" end="24" type="bool"/>
> >      <field name="Sampler L2 TLB Prefetch Enable Mask" start="25" end="25" type="bool"/>
> > -    <field name="Sampler Set Remapping for 3D Disable Mask" start="27" end="27" type="bool"/>
> > +    <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters Mask" start="26" end="26" type="bool"/>
> >      <field name="MSAA Compression Plane Number Threshold for eLLC Mask" start="28" end="30" type="uint"/>
> > -    <field name="Sampler L2 Disable Mask" start="31" end="31" type="bool"/>
> > +    <field name="Disable Repacking for Compression Mask" start="31" end="31" type="bool"/>
> >    </register>
> >
> >    <register name="CACHE_MODE_1" length="1" num="0x7004">
> > diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
> > index 21b8cd648d4..412faac9e52 100644
> > --- a/src/intel/vulkan/genX_state.c
> > +++ b/src/intel/vulkan/genX_state.c
> > @@ -225,6 +225,24 @@ genX(init_device_state)(struct anv_device *device)
> >     }
> >  #endif
> >
> > +#if GEN_GEN >= 11
> > +   /* needed to disable replacking to keep the compatibility with
> > +    * decompressing mechanism in display controller.
> > +    */
> > +   if (device->info.need_disable_ccs_repack) {
> > +      uint32_t cache_mode_0;
> > +      anv_pack_struct(&cache_mode_0,
> > +                      GENX(CACHE_MODE_0),
> > +                      .DisableRepackingforCompression = true,
> > +                      .DisableRepackingforCompressionMask = true);
> > +
> > +      anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
> > +         lri.RegisterOffset = GENX(CACHE_MODE_0_num);
> > +         lri.DataDWord      = cache_mode_0;
> > +      }
> > +   }
> > +#endif
> > +
> >     /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
> >      * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
> >      *
> > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> > index 17bca1991f1..e8507b7e5ff 100644
> > --- a/src/mesa/drivers/dri/i965/brw_defines.h
> > +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> > @@ -1576,6 +1576,7 @@ enum brw_pixel_shader_coverage_mask_mode {
> >  # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
> >  # define GEN8_HIZ_PMA_MASK_BITS \
> >     REG_MASK(GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE)
> > +# define GEN11_DISABLE_REPACKING_FOR_COMPRESSION (1 << 15)
> >
> >  #define GEN7_GT_MODE                    0x7008
> >  # define GEN9_SUBSLICE_HASHING_8x8      (0 << 8)
> > diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
> > index 938b9defeda..8395688c793 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> > +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> > @@ -121,6 +121,15 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
> >                                 REG_MASK(GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE));
> >     }
> >
> > +   /* needed to disable replacking to keep the compatibility with
> > +    * decompressing mechanism in display controller.
> > +    */
> > +   if (devinfo->need_disable_ccs_repack) {
> > +      brw_load_register_imm32(brw, GEN7_CACHE_MODE_0,
> > +                              GEN11_DISABLE_REPACKING_FOR_COMPRESSION |
> > +                              REG_MASK(GEN11_DISABLE_REPACKING_FOR_COMPRESSION));
> > +   }
> > +
> >     if (devinfo->gen == 10 || devinfo->gen == 11) {
> >        /* From gen10 workaround table in h/w specs:
> >         *
> > --
> > 2.17.1
> >