[01/23] drm/i915/icl: Add support to read out the TBT PLL HW state

Submitted by Imre Deak on June 4, 2019, 2:58 p.m.

Details

Message ID 20190604145826.16424-2-imre.deak@intel.com
State New
Headers show
Series "drm/i915: Fix TypeC port mode switching" ( rev: 2 1 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Imre Deak June 4, 2019, 2:58 p.m.
Add support to read out the TBT PLL HW state.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fc47ed0247c5..26474788b7b2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9859,13 +9859,20 @@  static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
 	enum intel_dpll_id id;
 	u32 temp;
 
-	/* TODO: TBT pll not implemented. */
 	if (intel_port_is_combophy(dev_priv, port)) {
 		temp = I915_READ(DPCLKA_CFGCR0_ICL) &
 		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
 		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
 	} else if (intel_port_is_tc(dev_priv, port)) {
-		id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
+		u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
+
+		if (clk_sel == DDI_CLK_SEL_MG) {
+			id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
+								    port));
+		} else {
+			WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
+			id = DPLL_ID_ICL_TBTPLL;
+		}
 	} else {
 		WARN(1, "Invalid port %x\n", port);
 		return;

Comments

On Tue, 2019-06-04 at 17:58 +0300, Imre Deak wrote:
> Add support to read out the TBT PLL HW state.


Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


> 

> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>

> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>

> Cc: Lucas De Marchi <lucas.demarchi@intel.com>

> Signed-off-by: Imre Deak <imre.deak@intel.com>

> ---

>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++--

>  1 file changed, 9 insertions(+), 2 deletions(-)

> 

> diff --git a/drivers/gpu/drm/i915/intel_display.c

> b/drivers/gpu/drm/i915/intel_display.c

> index fc47ed0247c5..26474788b7b2 100644

> --- a/drivers/gpu/drm/i915/intel_display.c

> +++ b/drivers/gpu/drm/i915/intel_display.c

> @@ -9859,13 +9859,20 @@ static void icelake_get_ddi_pll(struct

> drm_i915_private *dev_priv,

>  	enum intel_dpll_id id;

>  	u32 temp;

>  

> -	/* TODO: TBT pll not implemented. */

>  	if (intel_port_is_combophy(dev_priv, port)) {

>  		temp = I915_READ(DPCLKA_CFGCR0_ICL) &

>  		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);

>  		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);

>  	} else if (intel_port_is_tc(dev_priv, port)) {

> -		id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,

> port));

> +		u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) &

> DDI_CLK_SEL_MASK;

> +

> +		if (clk_sel == DDI_CLK_SEL_MG) {

> +			id =

> icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,

> +								    por

> t));

> +		} else {

> +			WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);

> +			id = DPLL_ID_ICL_TBTPLL;

> +		}

>  	} else {

>  		WARN(1, "Invalid port %x\n", port);

>  		return;