[3/9] radeonsi: fixes for vec3 buffer stores in LLVM 9

Submitted by Marek Olšák on June 4, 2019, 12:02 a.m.

Details

Message ID 20190604000258.9143-3-maraeo@gmail.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Mesa

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Commit Message

Marek Olšák June 4, 2019, 12:02 a.m.
From: Marek Olšák <marek.olsak@amd.com>

---
 src/gallium/drivers/radeonsi/si_shader.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

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diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index e044e180778..3610ec90a89 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2621,21 +2621,26 @@  static void emit_streamout_output(struct si_shader_context *ctx,
 	}
 
 	/* Pack the output. */
 	LLVMValueRef vdata = NULL;
 
 	switch (num_comps) {
 	case 1: /* as i32 */
 		vdata = out[0];
 		break;
 	case 2: /* as v2i32 */
-	case 3: /* as v4i32 (aligned to 4) */
+	case 3: /* as v3i32 */
+		if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
+			vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
+			break;
+		}
+		/* as v4i32 (aligned to 4) */
 		out[3] = LLVMGetUndef(ctx->i32);
 		/* fall through */
 	case 4: /* as v4i32 */
 		vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
 		break;
 	}
 
 	ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
 				    vdata, num_comps,
 				    so_write_offsets[buf_idx],
@@ -3118,22 +3123,24 @@  static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
 		unsigned param_outer, param_inner;
 
 		buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
 		base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
 
 		param_outer = si_shader_io_get_unique_index_patch(
 				      TGSI_SEMANTIC_TESSOUTER, 0);
 		tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
 					LLVMConstInt(ctx->i32, param_outer, 0));
 
-		outer_vec = ac_build_gather_values(&ctx->ac, outer,
-						   util_next_power_of_two(outer_comps));
+		unsigned outer_vec_size =
+			ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
+				outer_comps : util_next_power_of_two(outer_comps);
+		outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
 
 		ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
 					    outer_comps, tf_outer_offset,
 					    base, 0, 1, 0, true, false);
 		if (inner_comps) {
 			param_inner = si_shader_io_get_unique_index_patch(
 					      TGSI_SEMANTIC_TESSINNER, 0);
 			tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
 					LLVMConstInt(ctx->i32, param_inner, 0));