[v6,2/8] drm/i915: vgpu shared memory setup for pv optimization

Submitted by Xiaolin Zhang on June 3, 2019, 6:02 a.m.

Details

Message ID 1559541769-25279-3-git-send-email-xiaolin.zhang@intel.com
State New
Headers show
Series "i915 vgpu PV to improve vgpu performance" ( rev: 1 ) in Intel GVT devel

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Commit Message

Xiaolin Zhang June 3, 2019, 6:02 a.m.
To enable vgpu pv features, we need to setup a shared memory page
which will be used for data exchange directly accessed between both
guest and backend i915 driver to avoid emulation trap cost.

guest i915 will allocate this page memory and then pass it's physical
address to backend i915 driver through PVINFO register so that backend i915
driver can access this shared page meory without any trap cost with the
help form hyperviser's read guest gpa functionality.

guest i915 will send VGT_G2V_SHARED_PAGE_SETUP notification to host GVT
once shared memory setup finished.

the layout of the shared_page also defined as well in this patch which
is used for pv features implementation.

v0: RFC.
v1: addressed RFC comment to move both shared_page_lock and shared_page
to i915_virtual_gpu structure.
v2: packed i915_virtual_gpu structure.
v3: added SHARED_PAGE_SETUP g2v notification for pv shared_page setup
v4: added intel_vgpu_setup_shared_page() in i915_vgpu_pv.c.
v5: per engine desc data in shared memory.
v6: added version support in shared memory (Zhenyu).

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    |  3 ++-
 drivers/gpu/drm/i915/i915_pvinfo.h |  5 +++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 48 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_vgpu.h   | 31 ++++++++++++++++++++++++
 4 files changed, 85 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2bb38b4..9ccf37b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1244,7 +1244,8 @@  struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
 	u32 pv_caps;
-};
+	struct gvt_shared_page *shared_page;
+} __packed;
 
 /* used in computing the new watermarks state */
 struct intel_wm_config {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 619305a..4657bf7 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,7 @@  enum vgt_g2v_type {
 	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
 	VGT_G2V_EXECLIST_CONTEXT_CREATE,
 	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+	VGT_G2V_SHARED_PAGE_SETUP,
 	VGT_G2V_MAX,
 };
 
@@ -110,7 +111,9 @@  struct vgt_if {
 
 	u32 pv_caps;
 
-	u32  rsv7[0x200 - 25];    /* pad to one page */
+	u64 shared_page_gpa;
+
+	u32  rsv7[0x200 - 27];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index bb9f988..6020515 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -135,6 +135,9 @@  void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
 
 	for (i = 0; i < 4; i++)
 		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
+
+	if (dev_priv->vgpu.shared_page)
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
 }
 
 static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -286,6 +289,46 @@  int intel_vgt_balloon(struct drm_i915_private *dev_priv)
  * i915 vgpu PV support for Linux
  */
 
+/*
+ * shared_page setup for VGPU PV features
+ */
+static int intel_vgpu_setup_shared_page(struct drm_i915_private *dev_priv)
+{
+	struct intel_uncore *uncore = &dev_priv->uncore;
+	struct gvt_shared_page *shared_page;
+	u64 gpa;
+	u16 ver_maj, ver_min;
+
+	shared_page =  (struct gvt_shared_page *)get_zeroed_page(GFP_KERNEL);
+	if (!shared_page) {
+		DRM_INFO("out of memory for shared page memory\n");
+		return -ENOMEM;
+	}
+
+	/* pass guest memory pa address to GVT and then read back to verify */
+	gpa = __pa(shared_page);
+	__raw_uncore_write64(uncore, vgtif_reg(shared_page_gpa), gpa);
+	if (gpa != __raw_uncore_read64(uncore, vgtif_reg(shared_page_gpa))) {
+		DRM_INFO("vgpu: passed shared_page_gpa failed\n");
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
+		return -EIO;
+	}
+
+	__raw_uncore_write32(uncore, vgtif_reg(g2v_notify),
+			VGT_G2V_SHARED_PAGE_SETUP);
+	ver_maj = shared_page->ver_major;
+	ver_min = shared_page->ver_minor;
+	DRM_INFO("vgpu PV ver major %d and minor %d\n", ver_maj, ver_min);
+	if (ver_maj != PV_MAJOR || ver_min != PV_MINOR) {
+		DRM_INFO("vgpu: shared_page format incompatible\n");
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
+		return -EIO;
+	}
+
+	dev_priv->vgpu.shared_page = shared_page;
+	return 0;
+}
+
 /**
  * intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities
  * @dev_priv: i915 device private
@@ -305,9 +348,14 @@  bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv)
 	if (!intel_vgpu_has_pv_caps(dev_priv))
 		return false;
 
+	if (intel_vgpu_setup_shared_page(dev_priv))
+		goto err;
+
 	/* PV capability negotiation between PV guest and GVT */
 	gvt_pvcaps = __raw_uncore_read32(uncore, vgtif_reg(pv_caps));
 	pvcaps = dev_priv->vgpu.pv_caps & gvt_pvcaps;
+
+err:
 	dev_priv->vgpu.pv_caps = pvcaps;
 	__raw_uncore_write32(uncore, vgtif_reg(pv_caps), pvcaps);
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 91010fc..1030f5a 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -26,6 +26,37 @@ 
 
 #include "i915_pvinfo.h"
 
+/*
+ * A shared page(4KB) between gvt and VM, could be allocated by guest driver
+ * or a fixed location in PCI bar 0 region
+ */
+struct pv_ppgtt_update {
+	u64 pdp;
+	u64 start;
+	u64 length;
+	u32 cache_level;
+};
+
+struct pv_submission {
+	u64 descs[EXECLIST_MAX_PORTS];
+};
+
+#define PV_MAX_ENGINES_NUM (VECS1_HW + 1)
+#define PV_MAJOR		1
+#define PV_MINOR		0
+
+struct pv_buffer_desc {
+	struct pv_ppgtt_update pv_ppgtt;
+	struct pv_submission pv_elsp[PV_MAX_ENGINES_NUM];
+	bool submitted[PV_MAX_ENGINES_NUM];
+} __packed;
+
+struct gvt_shared_page {
+	u16 ver_major;
+	u16 ver_minor;
+	struct pv_buffer_desc buf;
+};
+
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
 bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv);