radeonsi: fix timestamp queries for compute-only contexts

Submitted by Marek Olšák on May 27, 2019, 8:10 p.m.

Details

Message ID 20190527201018.14649-1-maraeo@gmail.com
State New
Headers show
Series "radeonsi: fix timestamp queries for compute-only contexts" ( rev: 1 ) in Mesa

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Commit Message

Marek Olšák May 27, 2019, 8:10 p.m.
From: Marek Olšák <marek.olsak@amd.com>

---
 src/gallium/drivers/radeonsi/si_fence.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

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diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index 1d67fd87b90..6d914a1b184 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -72,31 +72,33 @@  void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
 		       struct si_resource *buf, uint64_t va,
 		       uint32_t new_fence, unsigned query_type)
 {
 	unsigned op = EVENT_TYPE(event) |
 		      EVENT_INDEX(event == V_028A90_CS_DONE ||
 				  event == V_028A90_PS_DONE ? 6 : 5) |
 		      event_flags;
 	unsigned sel = EOP_DST_SEL(dst_sel) |
 		       EOP_INT_SEL(int_sel) |
 		       EOP_DATA_SEL(data_sel);
+	bool compute_ib = !ctx->has_graphics ||
+			  cs == ctx->prim_discard_compute_cs;
 
-	if (ctx->chip_class >= GFX9 || cs == ctx->prim_discard_compute_cs) {
+	if (ctx->chip_class >= GFX9 ||
+	    (compute_ib && ctx->chip_class >= GFX7)) {
 		/* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
 		 * counters) must immediately precede every timestamp event to
 		 * prevent a GPU hang on GFX9.
 		 *
 		 * Occlusion queries don't need to do it here, because they
 		 * always do ZPASS_DONE before the timestamp.
 		 */
-		if (ctx->chip_class == GFX9 &&
-		    cs != ctx->prim_discard_compute_cs &&
+		if (ctx->chip_class == GFX9 && !compute_ib &&
 		    query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
 		    query_type != PIPE_QUERY_OCCLUSION_PREDICATE &&
 		    query_type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
 			struct si_resource *scratch = ctx->eop_bug_scratch;
 
 			assert(16 * ctx->screen->info.num_render_backends <=
 			       scratch->b.b.width0);
 			radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
 			radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
 			radeon_emit(cs, scratch->gpu_address);

Comments

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

On Mon, May 27, 2019 at 10:10 PM Marek Olšák <maraeo@gmail.com> wrote:
>
> From: Marek Olšák <marek.olsak@amd.com>
>
> ---
>  src/gallium/drivers/radeonsi/si_fence.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
> index 1d67fd87b90..6d914a1b184 100644
> --- a/src/gallium/drivers/radeonsi/si_fence.c
> +++ b/src/gallium/drivers/radeonsi/si_fence.c
> @@ -72,31 +72,33 @@ void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
>                        struct si_resource *buf, uint64_t va,
>                        uint32_t new_fence, unsigned query_type)
>  {
>         unsigned op = EVENT_TYPE(event) |
>                       EVENT_INDEX(event == V_028A90_CS_DONE ||
>                                   event == V_028A90_PS_DONE ? 6 : 5) |
>                       event_flags;
>         unsigned sel = EOP_DST_SEL(dst_sel) |
>                        EOP_INT_SEL(int_sel) |
>                        EOP_DATA_SEL(data_sel);
> +       bool compute_ib = !ctx->has_graphics ||
> +                         cs == ctx->prim_discard_compute_cs;
>
> -       if (ctx->chip_class >= GFX9 || cs == ctx->prim_discard_compute_cs) {
> +       if (ctx->chip_class >= GFX9 ||
> +           (compute_ib && ctx->chip_class >= GFX7)) {
>                 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
>                  * counters) must immediately precede every timestamp event to
>                  * prevent a GPU hang on GFX9.
>                  *
>                  * Occlusion queries don't need to do it here, because they
>                  * always do ZPASS_DONE before the timestamp.
>                  */
> -               if (ctx->chip_class == GFX9 &&
> -                   cs != ctx->prim_discard_compute_cs &&
> +               if (ctx->chip_class == GFX9 && !compute_ib &&
>                     query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
>                     query_type != PIPE_QUERY_OCCLUSION_PREDICATE &&
>                     query_type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
>                         struct si_resource *scratch = ctx->eop_bug_scratch;
>
>                         assert(16 * ctx->screen->info.num_render_backends <=
>                                scratch->b.b.width0);
>                         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
>                         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
>                         radeon_emit(cs, scratch->gpu_address);
> --
> 2.17.1
>
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