[15/15] nvc0: expose spirv support

Submitted by Karol Herbst on May 11, 2019, 2:07 p.m.

Details

Message ID 20190511140712.27095-16-kherbst@redhat.com
State New
Headers show
Series "Clover: support CL through SPIR-V" ( rev: 1 ) in Mesa

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Commit Message

Karol Herbst May 11, 2019, 2:07 p.m.
required for OpenCL

Signed-off-by: Karol Herbst <kherbst@redhat.com>
---
 src/gallium/drivers/nouveau/nouveau_screen.c   |  1 +
 src/gallium/drivers/nouveau/nouveau_screen.h   |  1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 14 +++++++++-----
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.h |  2 ++
 src/gallium/drivers/nouveau/nvc0/nvc0_state.c  | 10 ++++++++++
 5 files changed, 23 insertions(+), 5 deletions(-)

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diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c b/src/gallium/drivers/nouveau/nouveau_screen.c
index cbd45a1dc35..34d81e43893 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.c
+++ b/src/gallium/drivers/nouveau/nouveau_screen.c
@@ -187,6 +187,7 @@  nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev)
       nouveau_mesa_debug = atoi(nv_dbg);
 
    screen->prefer_nir = debug_get_bool_option("NV50_PROG_USE_NIR", false);
+   screen->force_enable_cl = debug_get_bool_option("NOUVEAU_ENABLE_CL", false);
 
    /* These must be set before any failure is possible, as the cleanup
     * paths assume they're responsible for deleting them.
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h b/src/gallium/drivers/nouveau/nouveau_screen.h
index 1302c608bec..5f74b6b8f72 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.h
+++ b/src/gallium/drivers/nouveau/nouveau_screen.h
@@ -69,6 +69,7 @@  struct nouveau_screen {
    struct disk_cache *disk_shader_cache;
 
    bool prefer_nir;
+   bool force_enable_cl;
 
 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
    union {
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index fe80c7e9103..f1352548280 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -400,9 +400,13 @@  nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
    switch (param) {
    case PIPE_SHADER_CAP_PREFERRED_IR:
       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
-   case PIPE_SHADER_CAP_SUPPORTED_IRS:
-      return 1 << PIPE_SHADER_IR_TGSI |
-             1 << PIPE_SHADER_IR_NIR;
+   case PIPE_SHADER_CAP_SUPPORTED_IRS: {
+      uint32_t irs = 1 << PIPE_SHADER_IR_TGSI |
+                     1 << PIPE_SHADER_IR_NIR;
+      if (screen->force_enable_cl)
+         irs |= 1 << PIPE_SHADER_IR_SPIRV;
+      return irs;
+   }
    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
@@ -895,7 +899,7 @@  nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 }
 
-static const nir_shader_compiler_options nir_options = {
+const nir_shader_compiler_options nvc0_nir_options = {
    .lower_fdiv = false,
    .lower_ffma = false,
    .fuse_ffma = false, /* nir doesn't track mad vs fma */
@@ -963,7 +967,7 @@  nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
                                  enum pipe_shader_type shader)
 {
    if (ir == PIPE_SHADER_IR_NIR)
-      return &nir_options;
+      return &nvc0_nir_options;
    return NULL;
 }
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index 392980562bd..6ae70e5b88f 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -241,4 +241,6 @@  nvc0_screen_tsc_free(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
    }
 }
 
+extern const struct nir_shader_compiler_options nvc0_nir_options;
+
 #endif
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
index 12e21862ee0..817c11de537 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -28,6 +28,7 @@ 
 
 #include "tgsi/tgsi_parse.h"
 #include "compiler/nir/nir.h"
+#include "compiler/spirv/nir_spirv.h"
 
 #include "nvc0/nvc0_stateobj.h"
 #include "nvc0/nvc0_context.h"
@@ -737,6 +738,15 @@  nvc0_cp_state_create(struct pipe_context *pipe,
    case PIPE_SHADER_IR_NIR:
       prog->pipe.ir.nir = (nir_shader *)cso->prog;
       break;
+   case PIPE_SHADER_IR_SPIRV: {
+      const struct pipe_binary_program_header *hdr =
+         (const struct pipe_binary_program_header*)cso->prog;
+      prog->pipe.type = PIPE_SHADER_IR_NIR;
+      prog->pipe.ir.nir = spirv_to_nir_cl((uint32_t*)hdr->blob, hdr->num_bytes / 4,
+                                          cso->entry_point,
+                                          &nvc0_nir_options);
+      break;
+   }
    default:
       assert(!"unsupported IR!");
       return NULL;