drm/i915/gen11: enable support for headerless msgs

Submitted by Dongwon Kim on April 24, 2019, 8:38 p.m.

Details

Message ID 20190424203857.7317-1-dongwon.kim@intel.com
State New
Headers show
Series "drm/i915/gen11: enable support for headerless msgs" ( rev: 2 ) in Intel GFX

Browsing this patch as part of:
"drm/i915/gen11: enable support for headerless msgs" rev 2 in Intel GFX
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Commit Message

Dongwon Kim April 24, 2019, 8:38 p.m.
Setting bit5 (headerless msg for preemptable GPGPU context) of SAMPLER_MODE
register to enable support for the headless msgs on gen11. None of existing
use cases will be affected by this as this change makes both types of message
- headerless and w/ header supported at the same time. It also complies with
the new recommendation for the default bit value for the next gen.

v2: rewrote commit message to include more information

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_lrc.c | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)

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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b74824f0b5b1..b45042f71c0a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8862,6 +8862,7 @@  enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
 
 #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
+#define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	(1 << 5)
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4e0a351bfbca..07c8fe2a5549 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1807,6 +1807,21 @@  static int gen8_init_common_ring(struct intel_engine_cs *engine)
 	return 0;
 }
 
+static int gen11_init_render_ring(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	int ret;
+
+	ret = gen8_init_common_ring(engine);
+	if (ret)
+		return ret;
+
+	/* allow headerless messages for pre-emptable GPGPU contexts */
+	I915_WRITE(GEN10_SAMPLER_MODE, _MASKED_BIT_ENABLE(GEN11_SAMPLER_ENABLE_HEADLESS_MSG));
+
+	return 0;
+}
+
 static void execlists_reset_prepare(struct intel_engine_cs *engine)
 {
 	struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -2516,6 +2531,9 @@  int logical_render_ring_init(struct intel_engine_cs *engine)
 		return ret;
 
 	/* Override some for render ring. */
+	if (INTEL_GEN(engine->i915) == 11)
+		engine->init_hw = gen11_init_render_ring;
+
 	engine->init_context = gen8_init_rcs_context;
 	engine->emit_flush = gen8_emit_flush_render;
 	engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;

Comments

Quoting Dongwon Kim (2019-04-24 21:38:57)
> Setting bit5 (headerless msg for preemptable GPGPU context) of SAMPLER_MODE
> register to enable support for the headless msgs on gen11. None of existing
> use cases will be affected by this as this change makes both types of message
> - headerless and w/ header supported at the same time. It also complies with
> the new recommendation for the default bit value for the next gen.
> 
> v2: rewrote commit message to include more information
> 
> Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_lrc.c | 18 ++++++++++++++++++
>  2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b74824f0b5b1..b45042f71c0a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8862,6 +8862,7 @@ enum {
>  #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC      (1 << 7)
>  
>  #define GEN10_SAMPLER_MODE             _MMIO(0xE18C)
> +#define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG    (1 << 5)
>  
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)         _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 4e0a351bfbca..07c8fe2a5549 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1807,6 +1807,21 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
>         return 0;
>  }
>  
> +static int gen11_init_render_ring(struct intel_engine_cs *engine)
> +{
> +       struct drm_i915_private *dev_priv = engine->i915;
> +       int ret;
> +
> +       ret = gen8_init_common_ring(engine);
> +       if (ret)
> +               return ret;
> +
> +       /* allow headerless messages for pre-emptable GPGPU contexts */
> +       I915_WRITE(GEN10_SAMPLER_MODE, _MASKED_BIT_ENABLE(GEN11_SAMPLER_ENABLE_HEADLESS_MSG));

But you didn't move this to icl_ctx_workarounds_init() where it will be
then checked by igt (making sure it remains set after resets and
resume).
-Chris