drm/i915/icl: Fix MG_DP_MODE() register programming

Submitted by Imre Deak on April 19, 2019, 7:10 a.m.

Details

Message ID 20190419071026.32370-1-imre.deak@intel.com
State Accepted
Commit 9c11b12184bb01d8ba2c48e655509b184f02c769
Headers show
Series "drm/i915/icl: Fix MG_DP_MODE() register programming" ( rev: 1 ) in Intel GFX

Browsing this patch as part of:
"drm/i915/icl: Fix MG_DP_MODE() register programming" rev 1 in Intel GFX
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Commit Message

Imre Deak April 19, 2019, 7:10 a.m.
Fix the order of lane, port parameters passed to the register macro.

Note that this was already partly fixed by commit
37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters order")

Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically consistent")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 24f9106efcc6..f181c26f62fd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2905,21 +2905,20 @@  static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum port port = dig_port->base.port;
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
-	i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
 	u32 val;
-	int i;
+	int ln;
 
 	if (tc_port == PORT_TC_NONE)
 		return;
 
-	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
-		val = I915_READ(mg_regs[i]);
+	for (ln = 0; ln < 2; ln++) {
+		val = I915_READ(MG_DP_MODE(ln, port));
 		val |= MG_DP_MODE_CFG_TR2PWR_GATING |
 		       MG_DP_MODE_CFG_TRPWR_GATING |
 		       MG_DP_MODE_CFG_CLNPWR_GATING |
 		       MG_DP_MODE_CFG_DIGPWR_GATING |
 		       MG_DP_MODE_CFG_GAONPWR_GATING;
-		I915_WRITE(mg_regs[i], val);
+		I915_WRITE(MG_DP_MODE(ln, port), val);
 	}
 
 	val = I915_READ(MG_MISC_SUS0(tc_port));
@@ -2938,21 +2937,20 @@  static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum port port = dig_port->base.port;
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
-	i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
 	u32 val;
-	int i;
+	int ln;
 
 	if (tc_port == PORT_TC_NONE)
 		return;
 
-	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
-		val = I915_READ(mg_regs[i]);
+	for (ln = 0; ln < 2; ln++) {
+		val = I915_READ(MG_DP_MODE(ln, port));
 		val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
 			 MG_DP_MODE_CFG_TRPWR_GATING |
 			 MG_DP_MODE_CFG_CLNPWR_GATING |
 			 MG_DP_MODE_CFG_DIGPWR_GATING |
 			 MG_DP_MODE_CFG_GAONPWR_GATING);
-		I915_WRITE(mg_regs[i], val);
+		I915_WRITE(MG_DP_MODE(ln, port), val);
 	}
 
 	val = I915_READ(MG_MISC_SUS0(tc_port));

Comments


On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote:
> On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> > Fix the order of lane, port parameters passed to the register macro.
> > 
> > Note that this was already partly fixed by commit
> > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right
> > parameters order")
> > 
> > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically
> > consistent")
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++----------
> >  1 file changed, 8 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 24f9106efcc6..f181c26f62fd 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2905,21 +2905,20 @@ static void
> > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
> >  	struct drm_i915_private *dev_priv = to_i915(dig_port-
> > >base.base.dev);
> >  	enum port port = dig_port->base.port;
> >  	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > -	i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1,
> > port) };
> >  	u32 val;
> > -	int i;
> > +	int ln;
> >  
> >  	if (tc_port == PORT_TC_NONE)
> >  		return;
> >  
> > -	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > -		val = I915_READ(mg_regs[i]);
> > +	for (ln = 0; ln < 2; ln++) {
> > +		val = I915_READ(MG_DP_MODE(ln, port));
> >  		val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> >  		       MG_DP_MODE_CFG_TRPWR_GATING |
> >  		       MG_DP_MODE_CFG_CLNPWR_GATING |
> >  		       MG_DP_MODE_CFG_DIGPWR_GATING |
> >  		       MG_DP_MODE_CFG_GAONPWR_GATING;
> > -		I915_WRITE(mg_regs[i], val);
> > +		I915_WRITE(MG_DP_MODE(ln, port), val);
> >  	}
> >  
> >  	val = I915_READ(MG_MISC_SUS0(tc_port));
> > @@ -2938,21 +2937,20 @@ static void
> > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> >  	struct drm_i915_private *dev_priv = to_i915(dig_port-
> > >base.base.dev);
> >  	enum port port = dig_port->base.port;
> >  	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > -	i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> > 1) };
> 
> I would split this fix from the change dropping mg_regs or at least
> tell that while you were fixing it you changed the way it reads
> each MG_DP_MODE line.

I don't think it's worth a separate patch, since it's a small change
and quite obvious what and how changed. I can add a note to the commit
message about making things simpler.

> 
> 
> >  	u32 val;
> > -	int i;
> > +	int ln;
> >  
> >  	if (tc_port == PORT_TC_NONE)
> >  		return;
> >  
> > -	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > -		val = I915_READ(mg_regs[i]);
> > +	for (ln = 0; ln < 2; ln++) {
> > +		val = I915_READ(MG_DP_MODE(ln, port));
> >  		val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> >  			 MG_DP_MODE_CFG_TRPWR_GATING |
> >  			 MG_DP_MODE_CFG_CLNPWR_GATING |
> >  			 MG_DP_MODE_CFG_DIGPWR_GATING |
> >  			 MG_DP_MODE_CFG_GAONPWR_GATING);
> > -		I915_WRITE(mg_regs[i], val);
> > +		I915_WRITE(MG_DP_MODE(ln, port), val);
> >  	}
> >  
> >  	val = I915_READ(MG_MISC_SUS0(tc_port));

On Fri, Apr 19, 2019 at 07:29:05PM +0300, Souza, Jose wrote:
> On Fri, 2019-04-19 at 19:04 +0300, Imre Deak wrote:
> > On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote:
> > > On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> > > > Fix the order of lane, port parameters passed to the register
> > > > macro.
> > > > 
> > > > Note that this was already partly fixed by commit
> > > > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right
> > > > parameters order")
> > > > 
> > > > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically
> > > > consistent")
> > > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++----------
> > > >  1 file changed, 8 insertions(+), 10 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > > index 24f9106efcc6..f181c26f62fd 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > @@ -2905,21 +2905,20 @@ static void
> > > > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
> > > >  	struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > > > base.base.dev);
> > > >  	enum port port = dig_port->base.port;
> > > >  	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > > > -	i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1,
> > > > port) };
> > > >  	u32 val;
> > > > -	int i;
> > > > +	int ln;
> > > >  
> > > >  	if (tc_port == PORT_TC_NONE)
> > > >  		return;
> > > >  
> > > > -	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > > > -		val = I915_READ(mg_regs[i]);
> > > > +	for (ln = 0; ln < 2; ln++) {
> > > > +		val = I915_READ(MG_DP_MODE(ln, port));
> > > >  		val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> > > >  		       MG_DP_MODE_CFG_TRPWR_GATING |
> > > >  		       MG_DP_MODE_CFG_CLNPWR_GATING |
> > > >  		       MG_DP_MODE_CFG_DIGPWR_GATING |
> > > >  		       MG_DP_MODE_CFG_GAONPWR_GATING;
> > > > -		I915_WRITE(mg_regs[i], val);
> > > > +		I915_WRITE(MG_DP_MODE(ln, port), val);
> > > >  	}
> > > >  
> > > >  	val = I915_READ(MG_MISC_SUS0(tc_port));
> > > > @@ -2938,21 +2937,20 @@ static void
> > > > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> > > >  	struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > > > base.base.dev);
> > > >  	enum port port = dig_port->base.port;
> > > >  	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > > > -	i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> > > > 1) };
> > > 
> > > I would split this fix from the change dropping mg_regs or at least
> > > tell that while you were fixing it you changed the way it reads
> > > each MG_DP_MODE line.
> > 
> > I don't think it's worth a separate patch, since it's a small change
> > and quite obvious what and how changed. I can add a note to the
> > commit
> > message about making things simpler.
> 
> I suggested split because this will probably be backported so would be
> nice to be as clean as possible but I'm also okay if you add it to the
> commit description.

No need to backport this, the regressing commit won't make it to 5.1.
Even if it had this fix would still go through -fixes since we're still
only in -rc5, and so we wouldn't need to backport anything. So this
change along with the rest of related macro param shuffling patches
won't appear until 5.2.

For the future: git fetch stable; git fetch linus-upstream followed by
git tag --contains <regressing commit> makes it easy to see if something
needs backporting.

> 
> > 
> > > 
> > > >  	u32 val;
> > > > -	int i;
> > > > +	int ln;
> > > >  
> > > >  	if (tc_port == PORT_TC_NONE)
> > > >  		return;
> > > >  
> > > > -	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > > > -		val = I915_READ(mg_regs[i]);
> > > > +	for (ln = 0; ln < 2; ln++) {
> > > > +		val = I915_READ(MG_DP_MODE(ln, port));
> > > >  		val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> > > >  			 MG_DP_MODE_CFG_TRPWR_GATING |
> > > >  			 MG_DP_MODE_CFG_CLNPWR_GATING |
> > > >  			 MG_DP_MODE_CFG_DIGPWR_GATING |
> > > >  			 MG_DP_MODE_CFG_GAONPWR_GATING);
> > > > -		I915_WRITE(mg_regs[i], val);
> > > > +		I915_WRITE(MG_DP_MODE(ln, port), val);
> > > >  	}
> > > >  
> > > >  	val = I915_READ(MG_MISC_SUS0(tc_port));
> > 
> >
On Fri, Apr 19, 2019 at 10:10:26AM +0300, Imre Deak wrote:
>Fix the order of lane, port parameters passed to the register macro.
>
>Note that this was already partly fixed by commit
>37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters order")
>
>Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically consistent")
>Cc: José Roberto de Souza <jose.souza@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Aditya Swarup <aditya.swarup@intel.com>
>Signed-off-by: Imre Deak <imre.deak@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi

>---
> drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++----------
> 1 file changed, 8 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>index 24f9106efcc6..f181c26f62fd 100644
>--- a/drivers/gpu/drm/i915/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/intel_ddi.c
>@@ -2905,21 +2905,20 @@ static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
> 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> 	enum port port = dig_port->base.port;
> 	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>-	i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
> 	u32 val;
>-	int i;
>+	int ln;
>
> 	if (tc_port == PORT_TC_NONE)
> 		return;
>
>-	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
>-		val = I915_READ(mg_regs[i]);
>+	for (ln = 0; ln < 2; ln++) {
>+		val = I915_READ(MG_DP_MODE(ln, port));
> 		val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> 		       MG_DP_MODE_CFG_TRPWR_GATING |
> 		       MG_DP_MODE_CFG_CLNPWR_GATING |
> 		       MG_DP_MODE_CFG_DIGPWR_GATING |
> 		       MG_DP_MODE_CFG_GAONPWR_GATING;
>-		I915_WRITE(mg_regs[i], val);
>+		I915_WRITE(MG_DP_MODE(ln, port), val);
> 	}
>
> 	val = I915_READ(MG_MISC_SUS0(tc_port));
>@@ -2938,21 +2937,20 @@ static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> 	enum port port = dig_port->base.port;
> 	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>-	i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
> 	u32 val;
>-	int i;
>+	int ln;
>
> 	if (tc_port == PORT_TC_NONE)
> 		return;
>
>-	for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
>-		val = I915_READ(mg_regs[i]);
>+	for (ln = 0; ln < 2; ln++) {
>+		val = I915_READ(MG_DP_MODE(ln, port));
> 		val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> 			 MG_DP_MODE_CFG_TRPWR_GATING |
> 			 MG_DP_MODE_CFG_CLNPWR_GATING |
> 			 MG_DP_MODE_CFG_DIGPWR_GATING |
> 			 MG_DP_MODE_CFG_GAONPWR_GATING);
>-		I915_WRITE(mg_regs[i], val);
>+		I915_WRITE(MG_DP_MODE(ln, port), val);
> 	}
>
> 	val = I915_READ(MG_MISC_SUS0(tc_port));
>-- 
>2.13.2
>
On Fri, Apr 19, 2019 at 08:55:02AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/icl: Fix MG_DP_MODE() register programming
> URL   : https://patchwork.freedesktop.org/series/59744/
> State : success

Thanks for the reviews, pushed to -dinq adding the not to the commit
message about simplifying things.

> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_5954_full -> Patchwork_12840_full
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**
> 
>   No regressions found.
> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_12840_full:
> 
> ### IGT changes ###
> 
> #### Suppressed ####
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * {igt@audio@hdmi-integrity-after-suspend}:
>     - shard-glk:          TIMEOUT -> FAIL
> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_12840_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_ctx_isolation@rcs0-s3:
>     - shard-apl:          PASS -> DMESG-WARN [fdo#108566] +3
> 
>   * igt@i915_pm_rpm@gem-execbuf-stress:
>     - shard-skl:          PASS -> INCOMPLETE [fdo#107803] / [fdo#107807]
> 
>   * igt@i915_pm_rpm@system-suspend:
>     - shard-kbl:          PASS -> INCOMPLETE [fdo#103665] / [fdo#107807]
> 
>   * igt@kms_busy@basic-flip-e:
>     - shard-apl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
> 
>   * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-f:
>     - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
> 
>   * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
>     - shard-glk:          PASS -> FAIL [fdo#104873]
> 
>   * igt@kms_dp_dsc@basic-dsc-enable-edp:
>     - shard-iclb:         PASS -> SKIP [fdo#109349]
> 
>   * igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
>     - shard-skl:          NOTRUN -> FAIL [fdo#103184]
> 
>   * igt@kms_fbcon_fbt@fbc-suspend:
>     - shard-skl:          PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1
> 
>   * igt@kms_force_connector_basic@prune-stale-modes:
>     - shard-apl:          NOTRUN -> SKIP [fdo#109271] +19
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
>     - shard-iclb:         PASS -> FAIL [fdo#103167] +3
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
>     - shard-snb:          NOTRUN -> SKIP [fdo#109271] +117
> 
>   * igt@kms_lease@atomic_implicit_crtc:
>     - shard-snb:          NOTRUN -> FAIL [fdo#110279]
> 
>   * igt@kms_lease@setcrtc_implicit_plane:
>     - shard-snb:          NOTRUN -> FAIL [fdo#110281]
> 
>   * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e:
>     - shard-snb:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
> 
>   * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
>     - shard-glk:          PASS -> SKIP [fdo#109271]
> 
>   * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
>     - shard-apl:          NOTRUN -> FAIL [fdo#108145]
> 
>   * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
>     - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2
> 
>   * igt@kms_plane_lowres@pipe-a-tiling-x:
>     - shard-iclb:         PASS -> FAIL [fdo#103166]
> 
>   * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
>     - shard-glk:          PASS -> SKIP [fdo#109271] / [fdo#109278]
> 
>   * igt@kms_psr@psr2_cursor_mmap_cpu:
>     - shard-iclb:         PASS -> SKIP [fdo#109441] +2
> 
>   * igt@kms_vrr@flip-suspend:
>     - shard-skl:          NOTRUN -> SKIP [fdo#109271] +40
> 
>   * igt@perf_pmu@rc6:
>     - shard-kbl:          PASS -> SKIP [fdo#109271]
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_softpin@noreloc-s3:
>     - shard-apl:          DMESG-WARN [fdo#108566] -> PASS +2
> 
>   * igt@kms_cursor_crc@cursor-64x64-suspend:
>     - shard-kbl:          DMESG-WARN [fdo#108566] -> PASS
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
>     - shard-iclb:         FAIL [fdo#103167] -> PASS +5
> 
>   * igt@kms_plane@pixel-format-pipe-c-planes:
>     - shard-glk:          SKIP [fdo#109271] -> PASS
> 
>   * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
>     - shard-skl:          FAIL [fdo#108145] -> PASS
> 
>   * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
>     - shard-glk:          SKIP [fdo#109271] / [fdo#109278] -> PASS +1
> 
>   * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
>     - shard-kbl:          DMESG-FAIL [fdo#105763] -> PASS
> 
>   * igt@kms_sysfs_edid_timing:
>     - shard-iclb:         FAIL [fdo#100047] -> PASS
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
>   [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
>   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
>   [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
>   [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
>   [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
>   [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
>   [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
>   [fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
>   [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
>   [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [fdo#110279]: https://bugs.freedesktop.org/show_bug.cgi?id=110279
>   [fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281
> 
> 
> Participating hosts (10 -> 9)
> ------------------------------
> 
>   Missing    (1): shard-hsw 
> 
> 
> Build changes
> -------------
> 
>   * Linux: CI_DRM_5954 -> Patchwork_12840
> 
>   CI_DRM_5954: a77e0dc060fcd1a2a09412067097685c5101589c @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_4957: a765aa108105804c19096554447ad0cb71f64fc3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_12840: d26cc79d0b12c09f18764d40b5a496230ad7fc4d @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12840/