radeon: Fix width align for hevc encode

Submitted by Zhang, Boyuan on April 17, 2019, 8:36 p.m.

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Message ID BL0PR12MB2529C122C1AFCE6F3B80A8BC87250@BL0PR12MB2529.namprd12.prod.outlook.com
State New
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Series "radeon: Fix width align for hevc encode" ( rev: 2 ) in Mesa

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Commit Message

Zhang, Boyuan April 17, 2019, 8:36 p.m.
Hi Lei,

You are right. The width alignment for HEVC encoding should be 64. This is actually a hardware requirement that we missed here. Thanks for catching it.

Just a small suggestion, can we use macros to define width alignment for hevc and h264 instead of the number 64 and 16? So that we can clearly notice the differences b/w this two codecs. Then we can replace the number with macros on radeon_vcn_enc.c:54&69, as well as radeon_vcn_enc_1_2.c:215

Thanks,
Boyuan


-----Original Message-----
From: mesa-dev <mesa-dev-bounces@lists.freedesktop.org> On Behalf Of Lei Zhou

Sent: April 15, 2019 2:24 AM
To: mesa-dev@lists.freedesktop.org
Subject: [Mesa-dev] [PATCH] radeon: Fix width align for hevc encode

Before, width is aligned to 16, we get 512x800 when encoding with 480x800, and conformance_window_flag=0 in sps.

Signed-off-by: Lei Zhou <zhoulei@kylinos.cn>

---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 2 +-  src/gallium/drivers/radeon/radeon_vcn_enc.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

--
2.21.0



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diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c b/src/gallium/drivers/radeon/radeon_uvd_enc.c
index 3164dbb2c20..f0bf756ec50 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -66,7 +66,7 @@  radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
       || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
    enc->enc_pic.crop_left = 0;
    enc->enc_pic.crop_right =
-      (align(enc->base.width, 16) - enc->base.width) / 2;
+      (align(enc->base.width, 64) - enc->base.width) / 2;
    enc->enc_pic.crop_top = 0;
    enc->enc_pic.crop_bottom =
       (align(enc->base.height, 16) - enc->base.height) / 2; diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 7d64a28a405..248f4c7d99e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -66,7 +66,7 @@  static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_pic
       enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
                             (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
       enc->enc_pic.crop_left = 0;
-      enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
+      enc->enc_pic.crop_right = (align(enc->base.width, 64) - 
+ enc->base.width) / 2;
       enc->enc_pic.crop_top = 0;
       enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
       enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;

Comments

Hi Boyuan,

Thanks for your suggestions. I have split this patch to 2 patches, and resent to mesa-dev mailing list. 

> Hi Lei,
> 
> You are right. The width alignment for HEVC encoding should be 64. This is actually a hardware requirement that we missed here. Thanks for catching it.
> 
> Just a small suggestion, can we use macros to define width alignment for hevc and h264 instead of the number 64 and 16? So that we can clearly notice the differences b/w this two codecs. Then we can replace the number with macros on radeon_vcn_enc.c:54&69, as well as radeon_vcn_enc_1_2.c:215
> 
> Thanks,
> Boyuan
> 
> 
> -----Original Message-----
> From: mesa-dev <mesa-dev-bounces@lists.freedesktop.org> On Behalf Of Lei Zhou
> Sent: April 15, 2019 2:24 AM
> To: mesa-dev@lists.freedesktop.org
> Subject: [Mesa-dev] [PATCH] radeon: Fix width align for hevc encode
> 
> Before, width is aligned to 16, we get 512x800 when encoding with 480x800, and conformance_window_flag=0 in sps.
> 
> Signed-off-by: Lei Zhou <zhoulei@kylinos.cn>
> ---
>  src/gallium/drivers/radeon/radeon_uvd_enc.c | 2 +-  src/gallium/drivers/radeon/radeon_vcn_enc.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c b/src/gallium/drivers/radeon/radeon_uvd_enc.c
> index 3164dbb2c20..f0bf756ec50 100644
> --- a/src/gallium/drivers/radeon/radeon_uvd_enc.c
> +++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
> @@ -66,7 +66,7 @@ radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
>        || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
>     enc->enc_pic.crop_left = 0;
>     enc->enc_pic.crop_right =
> -      (align(enc->base.width, 16) - enc->base.width) / 2;
> +      (align(enc->base.width, 64) - enc->base.width) / 2;
>     enc->enc_pic.crop_top = 0;
>     enc->enc_pic.crop_bottom =
>        (align(enc->base.height, 16) - enc->base.height) / 2; diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c b/src/gallium/drivers/radeon/radeon_vcn_enc.c
> index 7d64a28a405..248f4c7d99e 100644
> --- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
> +++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
> @@ -66,7 +66,7 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_pic
>        enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
>                              (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
>        enc->enc_pic.crop_left = 0;
> -      enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
> +      enc->enc_pic.crop_right = (align(enc->base.width, 64) - 
> + enc->base.width) / 2;
>        enc->enc_pic.crop_top = 0;
>        enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
>        enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
> --
> 2.21.0
> 
> 
> 
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> mesa-dev@lists.freedesktop.org
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