[4/8] drm/i915: Add WaFlushCoherentL3CacheLinesAtContextSwitch:bdw

Submitted by Michel Thierry on July 15, 2014, 12:25 p.m.

Details

Message ID 1405427135-11377-5-git-send-email-michel.thierry@intel.com
State New, archived
Headers show

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Commit Message

Michel Thierry July 15, 2014, 12:25 p.m.
Coherent L3 cache lines are not getting flushed during context switch
which is causing issues.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 7 insertions(+)

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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44e7f34..aaadf4a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4708,6 +4708,9 @@  enum punit_power_well {
 #define GEN8_L3SQCREG1				0xb100
 #define  GEN8_L3SQCREG1_DEFAULT_VALUE	0x784000
 
+#define GEN8_L3SQCREG4				0xb118
+#define  GEN8_PIPELINE_FLUSH_COHERENT_LINES	(1<<21)
+
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6815680..8bde0aa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5490,6 +5490,10 @@  static void gen8_init_clock_gating(struct drm_device *dev)
 	/* WaDisableFfDopClockGating:bdw */
 	I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) &
 			~GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE);
+
+	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
+	I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+			GEN8_PIPELINE_FLUSH_COHERENT_LINES);
 }
 
 static void haswell_init_clock_gating(struct drm_device *dev)