tests/i915/gem_madvise.c: Add more mappings

Submitted by Antonio Argenziano on April 4, 2019, 8:32 p.m.

Details

Message ID 20190404203249.9937-1-antonio.argenziano@intel.com
State New
Headers show
Series "tests/i915/gem_madvise.c: Add more mappings" ( rev: 1 ) in IGT (deprecated)

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Commit Message

Antonio Argenziano April 4, 2019, 8:32 p.m.
Check madvise versus more memory mappings.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
---
 tests/i915/gem_madvise.c | 115 ++++++++++++++++++++++++++-------------
 1 file changed, 76 insertions(+), 39 deletions(-)

Patch hide | download patch | download mbox

diff --git a/tests/i915/gem_madvise.c b/tests/i915/gem_madvise.c
index 729a4d33..bcaaa22e 100644
--- a/tests/i915/gem_madvise.c
+++ b/tests/i915/gem_madvise.c
@@ -47,66 +47,103 @@  IGT_TEST_DESCRIPTION("Checks that the kernel reports EFAULT when trying to use"
  *
  */
 
-static jmp_buf jmp;
+static sigjmp_buf jmp;
 
 static void __attribute__((noreturn)) sigtrap(int sig)
 {
-	longjmp(jmp, sig);
+	siglongjmp(jmp, sig);
 }
 
+enum mode { CPU, WC, GTT };
+const char* modes[] = {[CPU] = "cpu", [WC] = "wc", [GTT] = "gtt"};
+
 static void
 dontneed_before_mmap(void)
 {
-	int fd = drm_open_driver(DRIVER_INTEL);
+	int fd;
 	uint32_t handle;
 	char *ptr;
 
-	handle = gem_create(fd, OBJECT_SIZE);
-	gem_madvise(fd, handle, I915_MADV_DONTNEED);
-	ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
-	close(fd);
-
-	signal(SIGSEGV, sigtrap);
-	signal(SIGBUS, sigtrap);
-	switch (setjmp(jmp)) {
-	case SIGBUS:
-		break;
-	case 0:
-		*ptr = 0;
-	default:
-		igt_assert(!"reached");
-		break;
+	for (unsigned mode = CPU; mode <= GTT; mode++) {
+		igt_debug("Mapping mode: %s\n", modes[mode]);
+
+		fd = drm_open_driver(DRIVER_INTEL);
+		handle = gem_create(fd, OBJECT_SIZE);
+		gem_madvise(fd, handle, I915_MADV_DONTNEED);
+
+		switch (mode) {
+			case GTT:
+				ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
+				break;
+			case CPU:
+				ptr = gem_mmap__cpu(fd, handle, 0, OBJECT_SIZE, PROT_READ | PROT_WRITE);
+				break;
+			case WC:
+				ptr = gem_mmap__wc(fd, handle, 0, OBJECT_SIZE, PROT_READ | PROT_WRITE);
+				break;
+		}
+
+		close(fd);
+
+		signal(SIGSEGV, sigtrap);
+		signal(SIGBUS, sigtrap);
+		switch (sigsetjmp(jmp, SIGBUS | SIGSEGV)) {
+			case SIGBUS:
+				break;
+			case 0:
+				*ptr = 0;
+			default:
+				igt_assert(!"reached");
+				break;
+		}
+		munmap(ptr, OBJECT_SIZE);
+		signal(SIGBUS, SIG_DFL);
+		signal(SIGSEGV, SIG_DFL);
 	}
-	munmap(ptr, OBJECT_SIZE);
-	signal(SIGBUS, SIG_DFL);
-	signal(SIGSEGV, SIG_DFL);
 }
 
 static void
 dontneed_after_mmap(void)
 {
-	int fd = drm_open_driver(DRIVER_INTEL);
+	int fd;
 	uint32_t handle;
 	char *ptr;
 
-	handle = gem_create(fd, OBJECT_SIZE);
-	ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
-	igt_assert(ptr);
-	gem_madvise(fd, handle, I915_MADV_DONTNEED);
-	close(fd);
-
-	signal(SIGBUS, sigtrap);
-	switch (setjmp(jmp)) {
-	case SIGBUS:
-		break;
-	case 0:
-		*ptr = 0;
-	default:
-		igt_assert(!"reached");
-		break;
+	for (unsigned mode = CPU; mode <= GTT; mode++) {
+		igt_debug("Mapping mode: %s\n", modes[mode]);
+
+		fd = drm_open_driver(DRIVER_INTEL);
+		handle = gem_create(fd, OBJECT_SIZE);
+
+		switch (mode) {
+			case GTT:
+				ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
+				break;
+			case CPU:
+				ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
+				break;
+			case WC:
+				ptr = gem_mmap__wc(fd, handle, 0, OBJECT_SIZE, PROT_READ | PROT_WRITE);
+				break;
+		}
+
+		igt_assert(ptr);
+		gem_madvise(fd, handle, I915_MADV_DONTNEED);
+		close(fd);
+
+		signal(SIGBUS, sigtrap);
+		switch (sigsetjmp(jmp, SIGBUS)) {
+			case SIGBUS:
+				break;
+			case 0:
+				*ptr = 0;
+			default:
+				igt_assert(!"reached");
+				break;
+		}
+		munmap(ptr, OBJECT_SIZE);
+		signal(SIGBUS, SIG_DFL);
 	}
-	munmap(ptr, OBJECT_SIZE);
-	signal(SIGBUS, SIG_DFL);
 }
 
 static void