| Message ID | 20190321120004.53012-1-michal.wajdeczko@intel.com |
|---|---|
| State | Accepted |
| Commit | 47c3b5e9b38b9da8db62d8c354be722852ea9d83 |
| Headers | show |
| Series |
"drm/i915/guc: Support for extended GuC notification messages"
( rev:
1
)
in
Intel GFX |
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index a59448a56f55..f2b4eaee8d52 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -484,17 +484,25 @@ void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc) spin_unlock(&guc->irq_lock); enable_rpm_wakeref_asserts(dev_priv); - intel_guc_to_host_process_recv_msg(guc, msg); + intel_guc_to_host_process_recv_msg(guc, &msg, 1); } -void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg) +int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, + const u32 *payload, u32 len) { + u32 msg; + + if (unlikely(!len)) + return -EPROTO; + /* Make sure to handle only enabled messages */ - msg &= guc->msg_enabled_mask; + msg = payload[0] & guc->msg_enabled_mask; if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER | INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) intel_guc_log_handle_flush_event(&guc->log); + + return 0; } int intel_guc_sample_forcewake(struct intel_guc *guc) diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 77ec1bd4df5a..2c59ff8d9f39 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -165,7 +165,8 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, void intel_guc_to_host_event_handler(struct intel_guc *guc); void intel_guc_to_host_event_handler_nop(struct intel_guc *guc); void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc); -void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg); +int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, + const u32 *payload, u32 len); int intel_guc_sample_forcewake(struct intel_guc *guc); int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); int intel_guc_suspend(struct intel_guc *guc); diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c index 79ddb8088311..dde1dc0d6e69 100644 --- a/drivers/gpu/drm/i915/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/intel_guc_ct.c @@ -701,14 +701,15 @@ static void ct_process_request(struct intel_guc_ct *ct, u32 action, u32 len, const u32 *payload) { struct intel_guc *guc = ct_to_guc(ct); + int ret; CT_DEBUG_DRIVER("CT: request %x %*ph\n", action, 4 * len, payload); switch (action) { case INTEL_GUC_ACTION_DEFAULT: - if (unlikely(len < 1)) + ret = intel_guc_to_host_process_recv_msg(guc, payload, len); + if (unlikely(ret)) goto fail_unexpected; - intel_guc_to_host_process_recv_msg(guc, *payload); break; default:
On 3/21/19 5:00 AM, Michal Wajdeczko wrote: > GuC may send notification messages with payload larger than > single u32. Prepare driver to accept longer messages. > Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To give a bit more context, for example the RESET_COMPLETE G2H will provide the engine class in the second dword. Daniele > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > Cc: Michal Winiarski <michal.winiarski@intel.com> > Cc: Tomasz Lis <tomasz.lis@intel.com> > --- > drivers/gpu/drm/i915/intel_guc.c | 14 +++++++++++--- > drivers/gpu/drm/i915/intel_guc.h | 3 ++- > drivers/gpu/drm/i915/intel_guc_ct.c | 5 +++-- > 3 files changed, 16 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c > index a59448a56f55..f2b4eaee8d52 100644 > --- a/drivers/gpu/drm/i915/intel_guc.c > +++ b/drivers/gpu/drm/i915/intel_guc.c > @@ -484,17 +484,25 @@ void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc) > spin_unlock(&guc->irq_lock); > enable_rpm_wakeref_asserts(dev_priv); > > - intel_guc_to_host_process_recv_msg(guc, msg); > + intel_guc_to_host_process_recv_msg(guc, &msg, 1); > } > > -void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg) > +int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, > + const u32 *payload, u32 len) > { > + u32 msg; > + > + if (unlikely(!len)) > + return -EPROTO; > + > /* Make sure to handle only enabled messages */ > - msg &= guc->msg_enabled_mask; > + msg = payload[0] & guc->msg_enabled_mask; > > if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER | > INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) > intel_guc_log_handle_flush_event(&guc->log); > + > + return 0; > } > > int intel_guc_sample_forcewake(struct intel_guc *guc) > diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h > index 77ec1bd4df5a..2c59ff8d9f39 100644 > --- a/drivers/gpu/drm/i915/intel_guc.h > +++ b/drivers/gpu/drm/i915/intel_guc.h > @@ -165,7 +165,8 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, > void intel_guc_to_host_event_handler(struct intel_guc *guc); > void intel_guc_to_host_event_handler_nop(struct intel_guc *guc); > void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc); > -void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg); > +int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, > + const u32 *payload, u32 len); > int intel_guc_sample_forcewake(struct intel_guc *guc); > int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); > int intel_guc_suspend(struct intel_guc *guc); > diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c > index 79ddb8088311..dde1dc0d6e69 100644 > --- a/drivers/gpu/drm/i915/intel_guc_ct.c > +++ b/drivers/gpu/drm/i915/intel_guc_ct.c > @@ -701,14 +701,15 @@ static void ct_process_request(struct intel_guc_ct *ct, > u32 action, u32 len, const u32 *payload) > { > struct intel_guc *guc = ct_to_guc(ct); > + int ret; > > CT_DEBUG_DRIVER("CT: request %x %*ph\n", action, 4 * len, payload); > > switch (action) { > case INTEL_GUC_ACTION_DEFAULT: > - if (unlikely(len < 1)) > + ret = intel_guc_to_host_process_recv_msg(guc, payload, len); > + if (unlikely(ret)) > goto fail_unexpected; > - intel_guc_to_host_process_recv_msg(guc, *payload); > break; > > default: >
Quoting Daniele Ceraolo Spurio (2019-03-22 23:29:13) > > > On 3/21/19 5:00 AM, Michal Wajdeczko wrote: > > GuC may send notification messages with payload larger than > > single u32. Prepare driver to accept longer messages. > > > > Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > To give a bit more context, for example the RESET_COMPLETE G2H will > provide the engine class in the second dword. And pushed, thanks for the patch. -Chris
GuC may send notification messages with payload larger than single u32. Prepare driver to accept longer messages. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> Cc: Tomasz Lis <tomasz.lis@intel.com> --- drivers/gpu/drm/i915/intel_guc.c | 14 +++++++++++--- drivers/gpu/drm/i915/intel_guc.h | 3 ++- drivers/gpu/drm/i915/intel_guc_ct.c | 5 +++-- 3 files changed, 16 insertions(+), 6 deletions(-)