[v5,1/2] drm/i915/gvt: remove the unused sreg

Submitted by Zhao, Yan Y on March 11, 2019, 1:40 a.m.

Details

Message ID 20190311014045.13977-1-yan.y.zhao@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 2 1 ) in Intel GVT devel

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Commit Message

Zhao, Yan Y March 11, 2019, 1:40 a.m.
code cleanup. sreg is not used now. remove it for code cleanness.

v3: remove unnecessary array_size in vreg's memory allocation (min he)
v2: do not allocate memory for sreg. (min he)

Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
---
 drivers/gpu/drm/i915/gvt/gvt.h      | 5 -----
 drivers/gpu/drm/i915/gvt/handlers.c | 5 +----
 drivers/gpu/drm/i915/gvt/mmio.c     | 8 ++------
 3 files changed, 3 insertions(+), 15 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index ef710e259726..a4fd979b3dad 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -94,7 +94,6 @@  struct intel_vgpu_fence {
 
 struct intel_vgpu_mmio {
 	void *vreg;
-	void *sreg;
 };
 
 #define INTEL_GVT_MAX_BAR_NUM 4
@@ -447,10 +446,6 @@  void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
 	(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
 #define vgpu_vreg64(vgpu, offset) \
 	(*(u64 *)(vgpu->mmio.vreg + (offset)))
-#define vgpu_sreg_t(vgpu, reg) \
-	(*(u32 *)(vgpu->mmio.sreg + i915_mmio_reg_offset(reg)))
-#define vgpu_sreg(vgpu, offset) \
-	(*(u32 *)(vgpu->mmio.sreg + (offset)))
 
 #define for_each_active_vgpu(gvt, vgpu, id) \
 	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index b5c0ac04925f..54bd0b033298 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3489,12 +3489,11 @@  int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
 		return mmio_info->read(vgpu, offset, pdata, bytes);
 	else {
 		u64 ro_mask = mmio_info->ro_mask;
-		u32 old_vreg = 0, old_sreg = 0;
+		u32 old_vreg = 0;
 		u64 data = 0;
 
 		if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
 			old_vreg = vgpu_vreg(vgpu, offset);
-			old_sreg = vgpu_sreg(vgpu, offset);
 		}
 
 		if (likely(!ro_mask))
@@ -3516,8 +3515,6 @@  int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
 
 			vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
 					| (vgpu_vreg(vgpu, offset) & mask);
-			vgpu_sreg(vgpu, offset) = (old_sreg & ~mask)
-					| (vgpu_sreg(vgpu, offset) & mask);
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index ed4df2f6d60b..a55178884d67 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -239,7 +239,6 @@  void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
 
 	if (dmlr) {
 		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
-		memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
 
 		vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
 
@@ -280,7 +279,6 @@  void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
 		 * touched
 		 */
 		memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
-		memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
 	}
 
 }
@@ -296,12 +294,10 @@  int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
 {
 	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
 
-	vgpu->mmio.vreg = vzalloc(array_size(info->mmio_size, 2));
+	vgpu->mmio.vreg = vzalloc(info->mmio_size);
 	if (!vgpu->mmio.vreg)
 		return -ENOMEM;
 
-	vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
-
 	intel_vgpu_reset_mmio(vgpu, true);
 
 	return 0;
@@ -315,5 +311,5 @@  int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
 {
 	vfree(vgpu->mmio.vreg);
-	vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;
+	vgpu->mmio.vreg = NULL;
 }

Comments

Looks good to me. Thanks.
Reviewed-by: He, Min <min.he@intel.com>


> -----Original Message-----

> From: intel-gvt-dev [mailto:intel-gvt-dev-bounces@lists.freedesktop.org] On

> Behalf Of Yan Zhao

> Sent: Monday, March 11, 2019 9:41 AM

> To: intel-gvt-dev@lists.freedesktop.org

> Cc: Zhao, Yan Y <yan.y.zhao@intel.com>

> Subject: [PATCH v5 1/2] drm/i915/gvt: remove the unused sreg

> 

> code cleanup. sreg is not used now. remove it for code cleanness.

> 

> v3: remove unnecessary array_size in vreg's memory allocation (min he)

> v2: do not allocate memory for sreg. (min he)

> 

> Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>

> ---

>  drivers/gpu/drm/i915/gvt/gvt.h      | 5 -----

>  drivers/gpu/drm/i915/gvt/handlers.c | 5 +----

>  drivers/gpu/drm/i915/gvt/mmio.c     | 8 ++------

>  3 files changed, 3 insertions(+), 15 deletions(-)

> 

> diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h

> index ef710e259726..a4fd979b3dad 100644

> --- a/drivers/gpu/drm/i915/gvt/gvt.h

> +++ b/drivers/gpu/drm/i915/gvt/gvt.h

> @@ -94,7 +94,6 @@ struct intel_vgpu_fence {

> 

>  struct intel_vgpu_mmio {

>  	void *vreg;

> -	void *sreg;

>  };

> 

>  #define INTEL_GVT_MAX_BAR_NUM 4

> @@ -447,10 +446,6 @@ void intel_vgpu_write_fence(struct intel_vgpu

> *vgpu,

>  	(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))

>  #define vgpu_vreg64(vgpu, offset) \

>  	(*(u64 *)(vgpu->mmio.vreg + (offset)))

> -#define vgpu_sreg_t(vgpu, reg) \

> -	(*(u32 *)(vgpu->mmio.sreg + i915_mmio_reg_offset(reg)))

> -#define vgpu_sreg(vgpu, offset) \

> -	(*(u32 *)(vgpu->mmio.sreg + (offset)))

> 

>  #define for_each_active_vgpu(gvt, vgpu, id) \

>  	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \

> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c

> b/drivers/gpu/drm/i915/gvt/handlers.c

> index b5c0ac04925f..54bd0b033298 100644

> --- a/drivers/gpu/drm/i915/gvt/handlers.c

> +++ b/drivers/gpu/drm/i915/gvt/handlers.c

> @@ -3489,12 +3489,11 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu

> *vgpu, unsigned int offset,

>  		return mmio_info->read(vgpu, offset, pdata, bytes);

>  	else {

>  		u64 ro_mask = mmio_info->ro_mask;

> -		u32 old_vreg = 0, old_sreg = 0;

> +		u32 old_vreg = 0;

>  		u64 data = 0;

> 

>  		if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset))

> {

>  			old_vreg = vgpu_vreg(vgpu, offset);

> -			old_sreg = vgpu_sreg(vgpu, offset);

>  		}

> 

>  		if (likely(!ro_mask))

> @@ -3516,8 +3515,6 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu

> *vgpu, unsigned int offset,

> 

>  			vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)

>  					| (vgpu_vreg(vgpu, offset) & mask);

> -			vgpu_sreg(vgpu, offset) = (old_sreg & ~mask)

> -					| (vgpu_sreg(vgpu, offset) & mask);

>  		}

>  	}

> 

> diff --git a/drivers/gpu/drm/i915/gvt/mmio.c

> b/drivers/gpu/drm/i915/gvt/mmio.c

> index ed4df2f6d60b..a55178884d67 100644

> --- a/drivers/gpu/drm/i915/gvt/mmio.c

> +++ b/drivers/gpu/drm/i915/gvt/mmio.c

> @@ -239,7 +239,6 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu,

> bool dmlr)

> 

>  	if (dmlr) {

>  		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);

> -		memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);

> 

>  		vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;

> 

> @@ -280,7 +279,6 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu,

> bool dmlr)

>  		 * touched

>  		 */

>  		memcpy(vgpu->mmio.vreg, mmio,

> GVT_GEN8_MMIO_RESET_OFFSET);

> -		memcpy(vgpu->mmio.sreg, mmio,

> GVT_GEN8_MMIO_RESET_OFFSET);

>  	}

> 

>  }

> @@ -296,12 +294,10 @@ int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)

>  {

>  	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;

> 

> -	vgpu->mmio.vreg = vzalloc(array_size(info->mmio_size, 2));

> +	vgpu->mmio.vreg = vzalloc(info->mmio_size);

>  	if (!vgpu->mmio.vreg)

>  		return -ENOMEM;

> 

> -	vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;

> -

>  	intel_vgpu_reset_mmio(vgpu, true);

> 

>  	return 0;

> @@ -315,5 +311,5 @@ int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)

>  void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)

>  {

>  	vfree(vgpu->mmio.vreg);

> -	vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;

> +	vgpu->mmio.vreg = NULL;

>  }

> --

> 2.17.1

> 

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