[v3,2/2] drm/i915/gvt: code refine of lri cmd parser

Submitted by Zhao, Yan Y on March 8, 2019, 8:39 a.m.

Details

Message ID 20190308083933.11235-1-yan.y.zhao@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GVT devel

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Commit Message

Zhao, Yan Y March 8, 2019, 8:39 a.m.
do not create a separate function intel_vgpu_mask_mmio_write()
but use intel_vgpu_mmio_reg_rw for consistency.

Fixes:
commit 6cef21a19649 ("drm/i915/gvt: update vreg on inhibit context lri
command")

Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c |  8 ++------
 drivers/gpu/drm/i915/gvt/handlers.c   | 24 ------------------------
 2 files changed, 2 insertions(+), 30 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 3592d04c33b2..37885e07c157 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -910,12 +910,8 @@  static int cmd_reg_handler(struct parser_exec_state *s,
 		/* check inhibit context */
 		if (ctx_sr_ctl & 1) {
 			u32 data = cmd_val(s, index + 1);
-
-			if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
-				intel_vgpu_mask_mmio_write(vgpu,
-							offset, &data, 4);
-			else
-				vgpu_vreg(vgpu, offset) = data;
+			intel_vgpu_mmio_reg_rw(s->vgpu, offset, &data,
+					4, false);
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 54bd0b033298..545154af93e9 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3401,30 +3401,6 @@  int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	return 0;
 }
 
-/**
- * intel_vgpu_mask_mmio_write - write mask register
- * @vgpu: a vGPU
- * @offset: access offset
- * @p_data: write data buffer
- * @bytes: access data length
- *
- * Returns:
- * Zero on success, negative error code if failed.
- */
-int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
-		void *p_data, unsigned int bytes)
-{
-	u32 mask, old_vreg;
-
-	old_vreg = vgpu_vreg(vgpu, offset);
-	write_vreg(vgpu, offset, p_data, bytes);
-	mask = vgpu_vreg(vgpu, offset) >> 16;
-	vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
-				(vgpu_vreg(vgpu, offset) & mask);
-
-	return 0;
-}
-
 /**
  * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
  * force-nopriv register