[15/23] drm/exynos: add GSCALER plane capability

Submitted by Andrzej Hajda on March 1, 2019, 12:20 p.m.

Details

Message ID 20190301122055.7135-16-a.hajda@samsung.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in DRI devel

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Commit Message

Andrzej Hajda March 1, 2019, 12:20 p.m.
This bit will indicate the plane is provided by GSCALER.
Tests shows that GSCALER does not like to convert from/to too small
buffers. Since exact constraints are not provided by documentation
rough estimate of 64 pixel has been applied.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
 drivers/gpu/drm/exynos/exynos_drm_drv.h   |  1 +
 drivers/gpu/drm/exynos/exynos_drm_plane.c | 14 +++++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

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diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 5d06e796dc80..7bdbac639b2b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -75,6 +75,7 @@  to_exynos_plane_state(struct drm_plane_state *state)
 #define EXYNOS_DRM_PLANE_CAP_TILE	(1 << 3)
 #define EXYNOS_DRM_PLANE_CAP_PIX_BLEND	(1 << 4)
 #define EXYNOS_DRM_PLANE_CAP_WIN_BLEND	(1 << 5)
+#define EXYNOS_DRM_PLANE_CAP_GSCALER	(1 << 6)
 
 struct exynos_drm_plane;
 struct exynos_drm_plane_ops {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 5f8f56b69369..89168157e1e2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -198,6 +198,11 @@  exynos_drm_plane_check_format(struct exynos_drm_plane_state *state)
 	return 0;
 }
 
+static bool is_in_range(int val, int min, int max)
+{
+	return (val >= min) && (val < max);
+}
+
 static int
 exynos_drm_plane_check_size(struct exynos_drm_plane_state *state)
 {
@@ -205,7 +210,7 @@  exynos_drm_plane_check_size(struct exynos_drm_plane_state *state)
 	bool width_ok = false, height_ok = false;
 
 	if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE)
-		return 0;
+		width_ok = height_ok = true;
 
 	if (state->src.w == state->crtc.w)
 		width_ok = true;
@@ -221,6 +226,13 @@  exynos_drm_plane_check_size(struct exynos_drm_plane_state *state)
 	    state->v_ratio == (1 << 15))
 		height_ok = true;
 
+	if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_GSCALER) {
+		width_ok = is_in_range(state->src.w, 64, 4800) &&
+			   is_in_range(state->crtc.w, 64, 4800);
+		height_ok = is_in_range(state->src.h, 64, 3344) &&
+			    is_in_range(state->crtc.h, 64, 3344);
+	}
+
 	if (width_ok && height_ok)
 		return 0;