[5/5] radeonsi: enable displayable DCC on Ravens

Submitted by Marek Olšák on Feb. 28, 2019, 9:20 p.m.

Details

Message ID 20190228212025.10805-6-maraeo@gmail.com
State New
Headers show
Series "RadeonSI: Displayable DCC for Ravens" ( rev: 1 ) in Mesa

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Commit Message

Marek Olšák Feb. 28, 2019, 9:20 p.m.
From: Marek Olšák <marek.olsak@amd.com>

---
 src/amd/common/ac_gpu_info.c                      | 8 ++++++++
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 4 ++++
 2 files changed, 12 insertions(+)

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diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index d890172227c..c53335bbb7d 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -451,20 +451,28 @@  bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	ib_align = MAX2(ib_align, dma.ib_start_alignment);
 	ib_align = MAX2(ib_align, uvd.ib_start_alignment);
 	ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
 	ib_align = MAX2(ib_align, vce.ib_start_alignment);
 	ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
 	ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
 	ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
 	assert(ib_align);
 	info->ib_start_alignment = ib_align;
 
+	if (info->drm_minor >= 31 &&
+	    (info->family == CHIP_RAVEN ||
+	     info->family == CHIP_RAVEN2)) {
+		if (info->num_render_backends == 1)
+			info->use_display_dcc_unaligned = true;
+		else
+			info->use_display_dcc_with_retile_blit = true;
+	}
 	return true;
 }
 
 void ac_compute_driver_uuid(char *uuid, size_t size)
 {
 	char amd_uuid[] = "AMD-MESA-DRV";
 
 	assert(size >= sizeof(amd_uuid));
 
 	memset(uuid, 0, size);
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
index d3a57f6b4f3..35a585a5693 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
@@ -38,20 +38,24 @@ 
 #include "radv_amdgpu_cs.h"
 #include "radv_amdgpu_bo.h"
 #include "radv_amdgpu_surface.h"
 
 static bool
 do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
 {
 	if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
 		return false;
 
+	/* temporary */
+	ws->info.use_display_dcc_unaligned = false;
+	ws->info.use_display_dcc_with_retile_blit = false;
+
 	ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
 	if (!ws->addrlib) {
 		fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
 		return false;
 	}
 
 	ws->info.num_sdma_rings = MIN2(ws->info.num_sdma_rings, MAX_RINGS_PER_TYPE);
 	ws->info.num_compute_rings = MIN2(ws->info.num_compute_rings, MAX_RINGS_PER_TYPE);
 
 	ws->use_ib_bos = ws->info.chip_class >= CIK;