[libdrm,2/2] tests/amdgpu: add memcpy dispatch test

Submitted by Cui, Flora on Feb. 28, 2019, 5:43 a.m.

Details

Message ID 1551332606-10141-2-git-send-email-flora.cui@amd.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Cui, Flora Feb. 28, 2019, 5:43 a.m.
add memcpy dispatch test for gfx9

Change-Id: If433434c5378f3b318209d4e28c19d7ce9cff1a2
Signed-off-by: Flora Cui <flora.cui@amd.com>
Tested-by: Rui Teng <rui.teng@amd.com>
---
 tests/amdgpu/basic_tests.c | 129 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 129 insertions(+)

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diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index d4b0faf..9d2cc95 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -305,6 +305,11 @@  static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
 
 static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
 
+static const uint32_t buffercopy_cs_shader_gfx9[] = {
+    0xD1FD0000, 0x04010C08, 0xE00C2000, 0x80000100,
+    0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF810000
+};
+
 int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
 			unsigned alignment, unsigned heap, uint64_t alloc_flags,
 			uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
@@ -2084,6 +2089,128 @@  static void amdgpu_memset_dispatch_test(uint32_t ip_type)
 
 	r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, bo_shader_size);
 	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+}
+
+static void amdgpu_memcpy_dispatch_test(uint32_t ip_type)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle bo_src, bo_dst, bo_shader, resources[3];
+	volatile unsigned char *ptr_dst;
+	void *ptr_shader;
+	void *ptr_src;
+	uint64_t mc_address_src, mc_address_dst, mc_address_shader;
+	amdgpu_va_handle va_src, va_dst, va_shader;
+	int i, j, r;
+	uint32_t *ptr;
+	int bo_dst_size = 16384;
+	int bo_shader_size = 4096;
+	struct amdgpu_cs_request ibs_request = {0};
+	struct amdgpu_cs_ib_info ib_info= {0};
+	uint32_t version, ring_id;
+	struct drm_amdgpu_info_hw_ip info;
+
+	r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &info);
+	CU_ASSERT_EQUAL(r, 0);
+
+	version = info.hw_ip_version_major;
+	if (version != 9) {
+		printf("\tSkip...memcpy dispatch test is only supported with gfx9\n");
+		return;
+	}
+
+	ptr = calloc(256, sizeof(*ptr));
+	CU_ASSERT_NOT_EQUAL(ptr, NULL);
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
+					AMDGPU_GEM_DOMAIN_VRAM, 0,
+					&bo_shader, &ptr_shader,
+					&mc_address_shader, &va_shader);
+	CU_ASSERT_EQUAL(r, 0);
+
+	memcpy(ptr_shader, buffercopy_cs_shader_gfx9, sizeof(buffercopy_cs_shader_gfx9));
+
+	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
+		r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+						AMDGPU_GEM_DOMAIN_VRAM, 0,
+						&bo_src, &ptr_src,
+						&mc_address_src, &va_src);
+		CU_ASSERT_EQUAL(r, 0);
+
+		r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+						AMDGPU_GEM_DOMAIN_VRAM, 0,
+						&bo_dst, &ptr_dst,
+						&mc_address_dst, &va_dst);
+		CU_ASSERT_EQUAL(r, 0);
+
+		memset(ptr_src, 0x55, bo_dst_size);
+
+		i = 0;
+		i += amdgpu_dispatch_init(ip_type, version, ptr + i);
+
+		/*  Issue commands to set cu mask used in current dispatch */
+		i += amdgpu_dispatch_write_cumask(ip_type, version, ptr + i);
+
+		/* Writes shader state to HW */
+		i += amdgpu_dispatch_write2hw(ip_type, version, ptr + i, mc_address_shader);
+
+		/* Write constant data */
+		/* Writes the texture resource constants data to the SGPRs */
+		ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+		ptr[i++] = 0x240;
+		ptr[i++] = mc_address_src;
+		ptr[i++] = (mc_address_src > 32) | 0x100000;
+		ptr[i++] = 0x400;
+		ptr[i++] = 0x74fac;
+		/* Writes the UAV constant data to the SGPRs. */
+		ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+		ptr[i++] = 0x244;
+		ptr[i++] = mc_address_dst;
+		ptr[i++] = (mc_address_dst > 32) | 0x100000;
+		ptr[i++] = 0x400;
+		ptr[i++] = 0x74fac;
+
+		/* dispatch direct command */
+		ptr[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
+		ptr[i++] = 0x10;
+		ptr[i++] = 1;
+		ptr[i++] = 1;
+		ptr[i++] = 1;
+
+		while (i & 7)
+			ptr[i++] =  0xffff1000; /* type3 nop packet */
+
+		resources[0] = bo_shader;
+		resources[1] = bo_src;
+		resources[2] = bo_dst;
+		amdgpu_test_exec_cs_helper(context_handle,
+					   ip_type, ring_id,
+					   i, ptr,
+					   3, resources,
+					   &ib_info, &ibs_request);
+
+		/* verify if memcpy test result meets with expected */
+		i = 0;
+		while(i < bo_dst_size) {
+			CU_ASSERT_EQUAL(ptr_dst[i++], 0x55);
+		}
+
+		r = amdgpu_bo_unmap_and_free(bo_src, va_src, mc_address_src, bo_dst_size);
+		CU_ASSERT_EQUAL(r, 0);
+		r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size);
+		CU_ASSERT_EQUAL(r, 0);
+	}
+
+	free(ptr);
+
+	r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, bo_shader_size);
+	CU_ASSERT_EQUAL(r, 0);
+
 	r = amdgpu_cs_ctx_free(context_handle);
 	CU_ASSERT_EQUAL(r, 0);
 }
@@ -2091,6 +2218,8 @@  static void amdgpu_memset_dispatch_test(uint32_t ip_type)
 static void amdgpu_dispatch_test(void)
 {
 	amdgpu_memset_dispatch_test(AMDGPU_HW_IP_GFX);
+	amdgpu_memcpy_dispatch_test(AMDGPU_HW_IP_GFX);
 
 	amdgpu_memset_dispatch_test(AMDGPU_HW_IP_COMPUTE);
+	amdgpu_memcpy_dispatch_test(AMDGPU_HW_IP_COMPUTE);
 }