[v4,24/40] intel/compiler: implement isign for int8

Submitted by Iago Toral Quiroga on Feb. 12, 2019, 11:55 a.m.

Details

Message ID 20190212115607.21467-25-itoral@igalia.com
State New
Headers show
Series "intel: VK_KHR_shader_float16_int8 implementation" ( rev: 16 15 14 13 12 11 10 9 8 7 6 ) in Mesa

Not browsing as part of any series.

Commit Message

Iago Toral Quiroga Feb. 12, 2019, 11:55 a.m.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---
 src/intel/compiler/brw_fs_nir.cpp | 25 +++++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

Patch hide | download patch | download mbox

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 3a6e4a2eb60..40c0481ac53 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -906,11 +906,28 @@  fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
        *  Predicated OR sets 1 if val is positive.
        */
       uint32_t bit_size = nir_dest_bit_size(instr->dest.dest);
-      assert(bit_size == 32 || bit_size == 16);
 
-      fs_reg zero = bit_size == 32 ? brw_imm_d(0) : brw_imm_w(0);
-      fs_reg one = bit_size == 32 ? brw_imm_d(1) : brw_imm_w(1);
-      fs_reg shift = bit_size == 32 ? brw_imm_d(31) : brw_imm_w(15);
+      fs_reg zero, one, shift;
+      switch (bit_size) {
+      case 32:
+         zero = brw_imm_d(0);
+         one = brw_imm_d(1);
+         shift = brw_imm_d(31);
+         break;
+      case 16:
+         zero = brw_imm_w(0);
+         one = brw_imm_w(1);
+         shift = brw_imm_w(15);
+         break;
+      case 8: {
+         zero = setup_imm_b(bld, 0);
+         one = setup_imm_b(bld, 1);
+         shift = setup_imm_b(bld, 7);
+         break;
+      }
+      default:
+         unreachable("unsupported bit-size");
+      };
 
       bld.CMP(bld.null_reg_d(), op[0], zero, BRW_CONDITIONAL_G);
       bld.ASR(result, op[0], shift);

Comments

We are now lowering isign in NIR so this patch is no longer needed.

Iago

On Tue, 2019-02-12 at 12:55 +0100, Iago Toral Quiroga wrote:
> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 25 +++++++++++++++++++++----
>  1 file changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index 3a6e4a2eb60..40c0481ac53 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -906,11 +906,28 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
>         *  Predicated OR sets 1 if val is positive.
>         */
>        uint32_t bit_size = nir_dest_bit_size(instr->dest.dest);
> -      assert(bit_size == 32 || bit_size == 16);
>  
> -      fs_reg zero = bit_size == 32 ? brw_imm_d(0) : brw_imm_w(0);
> -      fs_reg one = bit_size == 32 ? brw_imm_d(1) : brw_imm_w(1);
> -      fs_reg shift = bit_size == 32 ? brw_imm_d(31) : brw_imm_w(15);
> +      fs_reg zero, one, shift;
> +      switch (bit_size) {
> +      case 32:
> +         zero = brw_imm_d(0);
> +         one = brw_imm_d(1);
> +         shift = brw_imm_d(31);
> +         break;
> +      case 16:
> +         zero = brw_imm_w(0);
> +         one = brw_imm_w(1);
> +         shift = brw_imm_w(15);
> +         break;
> +      case 8: {
> +         zero = setup_imm_b(bld, 0);
> +         one = setup_imm_b(bld, 1);
> +         shift = setup_imm_b(bld, 7);
> +         break;
> +      }
> +      default:
> +         unreachable("unsupported bit-size");
> +      };
>  
>        bld.CMP(bld.null_reg_d(), op[0], zero, BRW_CONDITIONAL_G);
>        bld.ASR(result, op[0], shift);