drm/i915: Show the GEM trace if reset times out

Submitted by Chris Wilson on Feb. 12, 2019, 9:59 a.m.

Details

Message ID 20190212095908.21270-1-chris@chris-wilson.co.uk
State New
Series "drm/i915: Show the GEM trace if reset times out"
Headers show

Commit Message

Chris Wilson Feb. 12, 2019, 9:59 a.m.
As a debug aide for CI, include the GEM trace up to the point the reset
times out to try and work out where/why it is timing out.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem.c   |  1 +
 drivers/gpu/drm/i915/i915_reset.c | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c8c355bec091..44ce8f409e29 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4751,6 +4751,7 @@  int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 {
 	int ret;
 
+	GEM_TRACE("\n");
 	dev_priv->gt.last_init_time = ktime_get();
 
 	/* Double layer security blanket, see i915_gem_init() */
diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
index c1b53533ada6..7e389bbf27ff 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -628,6 +628,7 @@  int intel_reset_guc(struct drm_i915_private *i915)
  */
 static void reset_prepare_engine(struct intel_engine_cs *engine)
 {
+	GEM_TRACE("%s\n", engine->name);
 	/*
 	 * During the reset sequence, we must prevent the engine from
 	 * entering RC6. As the context state is undefined until we restart
@@ -670,11 +671,15 @@  static void reset_prepare(struct drm_i915_private *i915)
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 
+
+	GEM_TRACE("start\n");
 	for_each_engine(engine, i915, id)
 		reset_prepare_engine(engine);
 
 	intel_uc_sanitize(i915);
 	revoke_mmaps(i915);
+
+	GEM_TRACE("end\n");
 }
 
 static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
@@ -683,6 +688,8 @@  static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
 	enum intel_engine_id id;
 	int err;
 
+	GEM_TRACE("start\n");
+
 	/*
 	 * Everything depends on having the GTT running, so we need to start
 	 * there.
@@ -696,11 +703,14 @@  static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
 
 	i915_gem_restore_fences(i915);
 
+	GEM_TRACE("end\n");
+
 	return err;
 }
 
 static void reset_finish_engine(struct intel_engine_cs *engine)
 {
+	GEM_TRACE("%s\n", engine->name);
 	engine->reset.finish(engine);
 	intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
 }
@@ -749,8 +759,12 @@  static void reset_finish(struct drm_i915_private *i915)
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 
+	GEM_TRACE("start\n");
+
 	for_each_engine(engine, i915, id)
 		reset_finish_engine(engine);
+
+	GEM_TRACE("end\n");
 }
 
 static void reset_restart(struct drm_i915_private *i915)
@@ -768,6 +782,7 @@  static void reset_restart(struct drm_i915_private *i915)
 
 	arg = kmalloc(sizeof(*arg), GFP_KERNEL);
 	if (arg) {
+		GEM_TRACE("\n");
 		arg->i915 = i915;
 		INIT_WORK(&arg->work, restart_work);
 
@@ -941,6 +956,7 @@  static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
 {
 	int err, i;
 
+	GEM_TRACE("stalled_mask=%x\n", stalled_mask);
 	err = intel_gpu_reset(i915, ALL_ENGINES);
 	for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
 		msleep(10 * (i + 1));
@@ -1028,6 +1044,7 @@  void i915_reset(struct drm_i915_private *i915,
 	reset_finish(i915);
 	if (!i915_terminally_wedged(error))
 		reset_restart(i915);
+	GEM_TRACE("wedged? %s\n", yesno(i915_terminally_wedged(error)));
 	return;
 
 taint:
@@ -1356,6 +1373,7 @@  static void i915_wedge_me(struct work_struct *work)
 	dev_err(w->i915->drm.dev,
 		"%s timed out, cancelling all in-flight rendering.\n",
 		w->name);
+	GEM_TRACE_DUMP();
 	i915_gem_set_wedged(w->i915);
 }