[2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15

Submitted by Knott, William on Feb. 6, 2019, 7:35 p.m.


Message ID MN2PR12MB30401A4365C247051A060ABDE26F0@MN2PR12MB3040.namprd12.prod.outlook.com
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Series "Series without cover letter" ( rev: 3 ) in AMD X.Org drivers

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Commit Message

Knott, William Feb. 6, 2019, 7:35 p.m.
Hey Oak,

Interesting you should ask since this has been discussed a lot here recently.  So I didn't know until recently that the nbif routes doorbells only using 11:2.  So in each 4k page there is an area for the various doorbell recipients including cp gfx and compute.  

The doorbell upper/lower in the CP only control the setting of a doorbell updated bit and currently uses the full 27:2.  The CP also uses the full 27:2 to match the doorbell to a queue slot and initiate work.

So for your example if you set the ranges to 4k then the CP would not consider a 6k address to match the MEC range and would not actually trigger this doorbell updated logic.  This logic is only needed for waking up an idle scheduler and for power gating support.

We are changing the hardware in the doorbell range check to only look at 11:2 to match the nbif routing logic.  With the current hardware I am not even sure how you configure the range registers if you are using PASID in bits 27:12 of the doorbell.  The default for those registers says that compute gets everything from gfx (0x12) up to 3fffff.

How do you actually configure these currently, do you leave these defaults?   That seems like the only way to have it pseudo work without the coming hardware change. 


-----Original Message-----
From: Zeng, Oak 

Sent: Wednesday, February 06, 2019 10:23 AM
To: Zhao, Yong <Yong.Zhao@amd.com>; amd-gfx@lists.freedesktop.org; Knott, William <William.Knott@amd.com>; Yang, Alice (SRDC 3D) <Alice1.Yang@amd.com>
Cc: Zhao, Yong <Yong.Zhao@amd.com>
Subject: RE: [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15

+ Clint/Alice

Hi Clint,

We think CP_MEC_DOORBELL_RANGE_LOWER/UPPER registers are used by MEC to check whether a doorbell routed to MEC belongs to MEC, is this understanding correct? 

From the register spec, those registers are 27 bits. Does this mean MEC use all 27 bits to determine? For example, if we set lower/upper to [0, 4k], will a doorbell ring at 6K address be ignored by MEC?


-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhao, Yong

Sent: Tuesday, February 5, 2019 3:31 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhao, Yong <Yong.Zhao@amd.com>
Subject: [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15

Because CP can use all doorbells outside the ones reserved for SDMA, IH, and VCN, so the value set to CP_MEC_DOORBELL_RANGE_UPPER should be the maximal index possible in a page.

Change-Id: I402a56ce9a80e6c2ed2f96be431ae71ca88e73a4
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>

 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c        | 2 +-
 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 +++  drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++
 4 files changed, 8 insertions(+), 1 deletion(-)


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diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 5c8d04c353d0..90eca63605ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -73,6 +73,7 @@  struct amdgpu_doorbell_index {
 		} uvd_vce;
 	uint32_t max_assignment;
+	uint32_t last_idx;
 	/* Per engine SDMA doorbell size in dword */
 	uint32_t dw_range_per_sdma_eng;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 262ee3cf6f1c..0278e3ab6b94 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2998,7 +2998,7 @@  static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
 					(adev->doorbell_index.kiq * 2) << 2);
-					(adev->doorbell_index.userqueue_end * 2) << 2);
+				(adev->doorbell_index.last_idx * 2) << 2);
 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index d2409df2dde9..9eb8c9209231 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -88,5 +88,8 @@  void vega10_doorbell_index_init(struct amdgpu_device *adev)
 			- adev->doorbell_index.sdma_engine[0])
 			* adev->doorbell_index.entry_dw_size;
+	adev->doorbell_index.last_idx = PAGE_SIZE
+		/ (sizeof(uint32_t) * adev->doorbell_index.entry_dw_size) - 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index b28c5999d8f0..aa8c7699c689 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -91,5 +91,8 @@  void vega20_doorbell_index_init(struct amdgpu_device *adev)
 			- adev->doorbell_index.sdma_engine[0])
 			* adev->doorbell_index.entry_dw_size;
+	adev->doorbell_index.last_idx = PAGE_SIZE
+		/ (sizeof(uint32_t) * adev->doorbell_index.entry_dw_size) - 1;