[v2,2/2] drm/amd/powerplay: add override pcie parameters for Vega20 (v2)

Submitted by Kasiviswanathan, Harish on Feb. 5, 2019, 9:37 p.m.

Details

Message ID 1549402669-22313-2-git-send-email-Harish.Kasiviswanathan@amd.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Kasiviswanathan, Harish Feb. 5, 2019, 9:37 p.m.
v2: Fix SMU message format
    Send override message after SMU enable features

Change-Id: Ib880c83bc7aa12be370cf6619acfe66e12664c9c
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 45 +++++++++++++---------
 1 file changed, 27 insertions(+), 18 deletions(-)

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diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index da022ca..e1b1656 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -771,40 +771,49 @@  static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+/*
+ * Override PCIe link speed and link width for DPM Level 1. PPTable entries
+ * reflect the ASIC capabilities and not the system capabilities. For e.g.
+ * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch
+ * to DPM1, it fails as system doesn't support Gen4.
+ */
 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
-	uint32_t pcie_speed = 0, pcie_width = 0, pcie_arg;
+	uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 	int ret;
 
 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
-		pcie_speed = 16;
+		pcie_gen = 3;
 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-		pcie_speed = 8;
+		pcie_gen = 2;
 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-		pcie_speed = 5;
+		pcie_gen = 1;
 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
-		pcie_speed = 2;
+		pcie_gen = 0;
 
 	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)
-		pcie_width = 32;
+		pcie_width = 7;
 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
-		pcie_width = 16;
+		pcie_width = 6;
 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
-		pcie_width = 12;
+		pcie_width = 5;
 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
-		pcie_width = 8;
-	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 		pcie_width = 4;
+	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+		pcie_width = 3;
 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 		pcie_width = 2;
 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 		pcie_width = 1;
 
-	pcie_arg = pcie_width | (pcie_speed << 8);
-
+	/* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
+	 * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
+	 * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
+	 */
+	smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
-			PPSMC_MSG_OverridePcieParameters, pcie_arg);
+			PPSMC_MSG_OverridePcieParameters, smu_pcie_arg);
 	PP_ASSERT_WITH_CODE(!ret,
 		"[OverridePcieParameters] Attempt to override pcie params failed!",
 		return ret);
@@ -1611,11 +1620,6 @@  static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 			"[EnableDPMTasks] Failed to initialize SMC table!",
 			return result);
 
-	result = vega20_override_pcie_parameters(hwmgr);
-	PP_ASSERT_WITH_CODE(!result,
-			"[EnableDPMTasks] Failed to override pcie parameters!",
-			return result);
-
 	result = vega20_run_btc(hwmgr);
 	PP_ASSERT_WITH_CODE(!result,
 			"[EnableDPMTasks] Failed to run btc!",
@@ -1631,6 +1635,11 @@  static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 			"[EnableDPMTasks] Failed to enable all smu features!",
 			return result);
 
+	result = vega20_override_pcie_parameters(hwmgr);
+	PP_ASSERT_WITH_CODE(!result,
+			"[EnableDPMTasks] Failed to override pcie parameters!",
+			return result);
+
 	result = vega20_notify_smc_display_change(hwmgr);
 	PP_ASSERT_WITH_CODE(!result,
 			"[EnableDPMTasks] Failed to notify smc display change!",

Comments

Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com>


On 2019-02-05 4:37 p.m., Kasiviswanathan, Harish wrote:
> v2: Fix SMU message format

>      Send override message after SMU enable features

>

> Change-Id: Ib880c83bc7aa12be370cf6619acfe66e12664c9c

> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>

> ---

>   drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 45 +++++++++++++---------

>   1 file changed, 27 insertions(+), 18 deletions(-)

>

> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

> index da022ca..e1b1656 100644

> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

> @@ -771,40 +771,49 @@ static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)

>   	return 0;

>   }

>   

> +/*

> + * Override PCIe link speed and link width for DPM Level 1. PPTable entries

> + * reflect the ASIC capabilities and not the system capabilities. For e.g.

> + * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch

> + * to DPM1, it fails as system doesn't support Gen4.

> + */

>   static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)

>   {

>   	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);

> -	uint32_t pcie_speed = 0, pcie_width = 0, pcie_arg;

> +	uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;

>   	int ret;

>   

>   	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)

> -		pcie_speed = 16;

> +		pcie_gen = 3;

>   	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

> -		pcie_speed = 8;

> +		pcie_gen = 2;

>   	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)

> -		pcie_speed = 5;

> +		pcie_gen = 1;

>   	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)

> -		pcie_speed = 2;

> +		pcie_gen = 0;

>   

>   	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)

> -		pcie_width = 32;

> +		pcie_width = 7;

>   	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)

> -		pcie_width = 16;

> +		pcie_width = 6;

>   	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)

> -		pcie_width = 12;

> +		pcie_width = 5;

>   	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)

> -		pcie_width = 8;

> -	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)

>   		pcie_width = 4;

> +	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)

> +		pcie_width = 3;

>   	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)

>   		pcie_width = 2;

>   	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)

>   		pcie_width = 1;

>   

> -	pcie_arg = pcie_width | (pcie_speed << 8);

> -

> +	/* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1

> +	 * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4

> +	 * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32

> +	 */

> +	smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;

>   	ret = smum_send_msg_to_smc_with_parameter(hwmgr,

> -			PPSMC_MSG_OverridePcieParameters, pcie_arg);

> +			PPSMC_MSG_OverridePcieParameters, smu_pcie_arg);

>   	PP_ASSERT_WITH_CODE(!ret,

>   		"[OverridePcieParameters] Attempt to override pcie params failed!",

>   		return ret);

> @@ -1611,11 +1620,6 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)

>   			"[EnableDPMTasks] Failed to initialize SMC table!",

>   			return result);

>   

> -	result = vega20_override_pcie_parameters(hwmgr);

> -	PP_ASSERT_WITH_CODE(!result,

> -			"[EnableDPMTasks] Failed to override pcie parameters!",

> -			return result);

> -

>   	result = vega20_run_btc(hwmgr);

>   	PP_ASSERT_WITH_CODE(!result,

>   			"[EnableDPMTasks] Failed to run btc!",

> @@ -1631,6 +1635,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)

>   			"[EnableDPMTasks] Failed to enable all smu features!",

>   			return result);

>   

> +	result = vega20_override_pcie_parameters(hwmgr);

> +	PP_ASSERT_WITH_CODE(!result,

> +			"[EnableDPMTasks] Failed to override pcie parameters!",

> +			return result);

> +

>   	result = vega20_notify_smc_display_change(hwmgr);

>   	PP_ASSERT_WITH_CODE(!result,

>   			"[EnableDPMTasks] Failed to notify smc display change!",