[2/8] radeonsi: fix the top-of-pipe fence on SI

Submitted by Marek Olšák on Jan. 18, 2019, 4:43 p.m.

Details

Message ID 20190118164359.19461-3-maraeo@gmail.com
State New
Headers show
Series "RadeonSI: PKT3_WRITE_DATA for small uploads" ( rev: 1 ) in Mesa

Not browsing as part of any series.

Commit Message

Marek Olšák Jan. 18, 2019, 4:43 p.m.
From: Marek Olšák <marek.olsak@amd.com>

SI doesn't have MEM.
---
 src/gallium/drivers/radeonsi/si_fence.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

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diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index be394119af6..46d0289c90b 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -259,21 +259,22 @@  static void si_fine_fence_set(struct si_context *ctx,
 
 	*fence_ptr = 0;
 
 	uint64_t fence_va = fine->buf->gpu_address + fine->offset;
 
 	radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
 				  RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
 	if (flags & PIPE_FLUSH_TOP_OF_PIPE) {
 		struct radeon_cmdbuf *cs = ctx->gfx_cs;
 		radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-		radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
+		radeon_emit(cs, S_370_DST_SEL(ctx->chip_class >= CIK ? V_370_MEM
+								     : V_370_MEM_GRBM) |
 			S_370_WR_CONFIRM(1) |
 			S_370_ENGINE_SEL(V_370_PFP));
 		radeon_emit(cs, fence_va);
 		radeon_emit(cs, fence_va >> 32);
 		radeon_emit(cs, 0x80000000);
 	} else if (flags & PIPE_FLUSH_BOTTOM_OF_PIPE) {
 		si_cp_release_mem(ctx,
 				  V_028A90_BOTTOM_OF_PIPE_TS, 0,
 				  EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
 				  EOP_DATA_SEL_VALUE_32BIT,