radeonsi: disable render cond & pipeline stats for internal compute dispatches

Submitted by Marek Olšák on Jan. 17, 2019, 1:04 a.m.

Details

Message ID 20190117010445.32411-1-maraeo@gmail.com
State New
Headers show
Series "radeonsi: disable render cond & pipeline stats for internal compute dispatches" ( rev: 1 ) in Mesa

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Commit Message

Marek Olšák Jan. 17, 2019, 1:04 a.m.
From: Marek Olšák <marek.olsak@amd.com>

---
 src/gallium/drivers/radeonsi/si_compute_blit.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

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diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c
index c547d124507..bfc9fa4ece2 100644
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -51,39 +51,54 @@  unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
 		return 0;
 	case SI_COHERENCY_SHADER:
 		return SI_CONTEXT_INV_SMEM_L1 |
 		       SI_CONTEXT_INV_VMEM_L1 |
 		       (cache_policy == L2_BYPASS ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 	case SI_COHERENCY_CB_META:
 		return SI_CONTEXT_FLUSH_AND_INV_CB;
 	}
 }
 
+static void si_compute_internal_begin(struct si_context *sctx)
+{
+	sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
+	sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
+	sctx->render_cond_force_off = true;
+}
+
+static void si_compute_internal_end(struct si_context *sctx)
+{
+	sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
+	sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
+	sctx->render_cond_force_off = false;
+}
+
 static void si_compute_do_clear_or_copy(struct si_context *sctx,
 					struct pipe_resource *dst,
 					unsigned dst_offset,
 					struct pipe_resource *src,
 					unsigned src_offset,
 					unsigned size,
 					const uint32_t *clear_value,
 					unsigned clear_value_size,
 					enum si_coherency coher)
 {
 	struct pipe_context *ctx = &sctx->b;
 
 	assert(src_offset % 4 == 0);
 	assert(dst_offset % 4 == 0);
 	assert(size % 4 == 0);
 
 	assert(dst->target != PIPE_BUFFER || dst_offset + size <= dst->width0);
 	assert(!src || src_offset + size <= src->width0);
 
+	si_compute_internal_begin(sctx);
 	sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 		       SI_CONTEXT_CS_PARTIAL_FLUSH |
 		       si_get_flush_flags(sctx, coher, SI_COMPUTE_DST_CACHE_POLICY);
 
 	/* Save states. */
 	void *saved_cs = sctx->cs_shader_state.program;
 	struct pipe_shader_buffer saved_sb[2] = {};
 	si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, src ? 2 : 1, saved_sb);
 
 	/* The memory accesses are coalesced, meaning that the 1st instruction writes
@@ -150,20 +165,21 @@  static void si_compute_do_clear_or_copy(struct si_context *sctx,
 	enum si_cache_policy cache_policy = get_cache_policy(sctx, coher, size);
 	sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 		       (cache_policy == L2_BYPASS ? SI_CONTEXT_WRITEBACK_GLOBAL_L2 : 0);
 
 	if (cache_policy != L2_BYPASS)
 		r600_resource(dst)->TC_L2_dirty = true;
 
 	/* Restore states. */
 	ctx->bind_compute_state(ctx, saved_cs);
 	ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, src ? 2 : 1, saved_sb);
+	si_compute_internal_end(sctx);
 }
 
 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
 		     uint64_t offset, uint64_t size, uint32_t *clear_value,
 		     uint32_t clear_value_size, enum si_coherency coher)
 {
 	if (!size)
 		return;
 
 	unsigned clear_alignment = MIN2(clear_value_size, 4);
@@ -304,20 +320,21 @@  void si_compute_copy_image(struct si_context *sctx,
 	struct pipe_context *ctx = &sctx->b;
 	unsigned width = src_box->width;
 	unsigned height = src_box->height;
 	unsigned depth = src_box->depth;
 
 	unsigned data[] = {src_box->x, src_box->y, src_box->z, 0, dstx, dsty, dstz, 0};
 
 	if (width == 0 || height == 0)
 		return;
 
+	si_compute_internal_begin(sctx);
 	sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 		       si_get_flush_flags(sctx, SI_COHERENCY_SHADER, L2_STREAM);
 	si_make_CB_shader_coherent(sctx, dst->nr_samples, true);
 
 	struct pipe_constant_buffer saved_cb = {};
 	si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &saved_cb);
 
 	struct si_images *images = &sctx->images[PIPE_SHADER_COMPUTE];
 	struct pipe_image_view saved_image[2] = {0};
 	util_copy_image_view(&saved_image[0], &images->views[0]);
@@ -391,16 +408,17 @@  void si_compute_copy_image(struct si_context *sctx,
 	}
 
 	ctx->launch_grid(ctx, &info);
 
 	sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 		       (sctx->chip_class <= VI ? SI_CONTEXT_WRITEBACK_GLOBAL_L2 : 0) |
 		       si_get_flush_flags(sctx, SI_COHERENCY_SHADER, L2_STREAM);
 	ctx->bind_compute_state(ctx, saved_cs);
 	ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 2, saved_image);
 	ctx->set_constant_buffer(ctx, PIPE_SHADER_COMPUTE, 0, &saved_cb);
+	si_compute_internal_end(sctx);
 }
 
 void si_init_compute_blit_functions(struct si_context *sctx)
 {
 	sctx->b.clear_buffer = si_pipe_clear_buffer;
 }