[v3,07/42] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

Submitted by Iago Toral Quiroga on Jan. 15, 2019, 1:53 p.m.

Details

Message ID 20190115135414.2313-8-itoral@igalia.com
State New
Headers show
Series "intel: VK_KHR_shader_float16_int8 implementation" ( rev: 5 4 ) in Mesa

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Commit Message

Iago Toral Quiroga Jan. 15, 2019, 1:53 p.m.
Extended math doesn't support half-float on these generations.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---
 src/intel/compiler/brw_nir.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

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diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index f0fe7f870c2..3b2909da33e 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -631,6 +631,8 @@  lower_bit_size_callback(const nir_alu_instr *alu, UNUSED void *data)
    if (alu->dest.dest.ssa.bit_size != 16)
       return 0;
 
+   const struct brw_compiler *compiler = (const struct brw_compiler *) data;
+
    switch (alu->op) {
    case nir_op_idiv:
    case nir_op_imod:
@@ -643,6 +645,15 @@  lower_bit_size_callback(const nir_alu_instr *alu, UNUSED void *data)
    case nir_op_fround_even:
    case nir_op_ftrunc:
       return 32;
+   case nir_op_frcp:
+   case nir_op_frsq:
+   case nir_op_fsqrt:
+   case nir_op_fpow:
+   case nir_op_fexp2:
+   case nir_op_flog2:
+   case nir_op_fsin:
+   case nir_op_fcos:
+      return compiler->devinfo->gen < 9 ? 32 : 0;
    default:
       return 0;
    }
@@ -770,7 +781,7 @@  brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
       OPT(nir_opt_large_constants, NULL, 32);
    }
 
-   OPT(nir_lower_bit_size, lower_bit_size_callback, NULL);
+   OPT(nir_lower_bit_size, lower_bit_size_callback, (void *)compiler);
 
    if (is_scalar) {
       OPT(nir_lower_load_const_to_scalar);