[v3,15/42] intel/compiler: Extended Math is limited to SIMD8 on half-float

Submitted by Iago Toral Quiroga on Jan. 15, 2019, 1:53 p.m.

Details

Message ID 20190115135414.2313-16-itoral@igalia.com
State New
Headers show
Series "intel: VK_KHR_shader_float16_int8 implementation" ( rev: 5 4 ) in Mesa

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Commit Message

Iago Toral Quiroga Jan. 15, 2019, 1:53 p.m.
From the Skylake PRM, Extended Math Function:

  "The execution size must be no more than 8 when half-floats
   are used in source or destination operand."

Earlier generations do not support Extended Math with half-float.

v2:
 - Rewrite the code to make it more readable (Jason).

v3:
 - Use if-ladders or just if+return exclusively (Topi).

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (v1)
---
 src/intel/compiler/brw_fs.cpp | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

Patch hide | download patch | download mbox

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 0359eb079f7..0b3ec94e2d2 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5493,18 +5493,27 @@  get_lowered_simd_width(const struct gen_device_info *devinfo,
    case SHADER_OPCODE_EXP2:
    case SHADER_OPCODE_LOG2:
    case SHADER_OPCODE_SIN:
-   case SHADER_OPCODE_COS:
+   case SHADER_OPCODE_COS: {
       /* Unary extended math instructions are limited to SIMD8 on Gen4 and
-       * Gen6.
+       * Gen6. Extended Math Function is limited to SIMD8 with half-float.
        */
-      return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
-              devinfo->gen == 5 || devinfo->is_g4x ? MIN2(16, inst->exec_size) :
-              MIN2(8, inst->exec_size));
+      if (devinfo->gen == 6 || (devinfo->gen == 4 && !devinfo->is_g4x))
+         return MIN2(8, inst->exec_size);
+      if (inst->dst.type == BRW_REGISTER_TYPE_HF)
+         return MIN2(8, inst->exec_size);
+      return MIN2(16, inst->exec_size);
+   }
 
-   case SHADER_OPCODE_POW:
-      /* SIMD16 is only allowed on Gen7+. */
-      return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
-              MIN2(8, inst->exec_size));
+   case SHADER_OPCODE_POW: {
+      /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
+       * to SIMD8 with half-float
+       */
+      if (devinfo->gen < 7)
+         return MIN2(8, inst->exec_size);
+      if (inst->dst.type == BRW_REGISTER_TYPE_HF)
+         return MIN2(8, inst->exec_size);
+      return MIN2(16, inst->exec_size);
+   }
 
    case SHADER_OPCODE_INT_QUOTIENT:
    case SHADER_OPCODE_INT_REMAINDER:

Comments

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

On Tue, Jan 15, 2019 at 7:54 AM Iago Toral Quiroga <itoral@igalia.com>
wrote:

> From the Skylake PRM, Extended Math Function:
>
>   "The execution size must be no more than 8 when half-floats
>    are used in source or destination operand."
>
> Earlier generations do not support Extended Math with half-float.
>
> v2:
>  - Rewrite the code to make it more readable (Jason).
>
> v3:
>  - Use if-ladders or just if+return exclusively (Topi).
>
> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (v1)
> ---
>  src/intel/compiler/brw_fs.cpp | 27 ++++++++++++++++++---------
>  1 file changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
> index 0359eb079f7..0b3ec94e2d2 100644
> --- a/src/intel/compiler/brw_fs.cpp
> +++ b/src/intel/compiler/brw_fs.cpp
> @@ -5493,18 +5493,27 @@ get_lowered_simd_width(const struct
> gen_device_info *devinfo,
>     case SHADER_OPCODE_EXP2:
>     case SHADER_OPCODE_LOG2:
>     case SHADER_OPCODE_SIN:
> -   case SHADER_OPCODE_COS:
> +   case SHADER_OPCODE_COS: {
>        /* Unary extended math instructions are limited to SIMD8 on Gen4 and
> -       * Gen6.
> +       * Gen6. Extended Math Function is limited to SIMD8 with half-float.
>         */
> -      return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
> -              devinfo->gen == 5 || devinfo->is_g4x ? MIN2(16,
> inst->exec_size) :
> -              MIN2(8, inst->exec_size));
> +      if (devinfo->gen == 6 || (devinfo->gen == 4 && !devinfo->is_g4x))
> +         return MIN2(8, inst->exec_size);
> +      if (inst->dst.type == BRW_REGISTER_TYPE_HF)
> +         return MIN2(8, inst->exec_size);
> +      return MIN2(16, inst->exec_size);
> +   }
>
> -   case SHADER_OPCODE_POW:
> -      /* SIMD16 is only allowed on Gen7+. */
> -      return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
> -              MIN2(8, inst->exec_size));
> +   case SHADER_OPCODE_POW: {
> +      /* SIMD16 is only allowed on Gen7+. Extended Math Function is
> limited
> +       * to SIMD8 with half-float
> +       */
> +      if (devinfo->gen < 7)
> +         return MIN2(8, inst->exec_size);
> +      if (inst->dst.type == BRW_REGISTER_TYPE_HF)
> +         return MIN2(8, inst->exec_size);
> +      return MIN2(16, inst->exec_size);
> +   }
>
>     case SHADER_OPCODE_INT_QUOTIENT:
>     case SHADER_OPCODE_INT_REMAINDER:
> --
> 2.17.1
>
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